Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing
Reexamination Certificate
2011-04-26
2011-04-26
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Reexamination Certificate
active
07934182
ABSTRACT:
A delay distribution of a partial path that passes through a node to which a plurality of signals is input and for which an estimation in a statistical MAX is predicted to be large, that is present on a critical path having large influence on a circuit delay, and that has high possibility of improving the circuit delay, among nodes in a circuit graph is calculated by the Monte Carlo simulation instead of the block based simulation, thereby increasing speed and accuracy of delay analysis.
REFERENCES:
patent: 6662291 (2003-12-01), Hashimoto et al.
patent: 7350171 (2008-03-01), Zhang et al.
patent: 7689956 (2010-03-01), Ikeda
patent: 2006/0236279 (2006-10-01), Homma
patent: 2007/0113211 (2007-05-01), Zhang et al.
patent: 2008/0010558 (2008-01-01), Ikeda
patent: 2009/0306953 (2009-12-01), Liu et al.
patent: A 2006-268479 (2006-10-01), None
C. Visweswariah, et al., “First-Order Incremental Block-Based Statistical Timing Analysis,” In Proc. of the Design Automation Conf., pp. 331-336, 2004.
Hongliang Chang, et al., “Statistical Timing Analysis Considering Spatial Correlations Using Single Pert-Like Traversal,” In Proc. Intl. Conference on Computer Aided Design, pp. 621-625, 2003.
Ruiming Chen, et al., “New Block-Based Statistical Timing Analysis Approaches Without Moment Matching,” In. Proc. of the 12thAsia and South Pacific Design Automation Conference, pp. 462-267, 2007.
Aseem Agarwal, et al., “Statistical Timing Analysis using Bounds,” IEEE, In Proc. of Date, pp. 62-67, 2003.
Homma Katsumi
Nitta Izumi
Shibuya Toshiyuki
Chiang Jack
Fujitsu Limited
Fujitsu Patent Center
Parihar Suchin
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