Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
1998-09-28
2001-05-08
Thai, Tuan V. (Department: 2186)
Static information storage and retrieval
Interconnection arrangements
C365S189050, C365S230020, C365S233100, C711S104000, C711S105000
Reexamination Certificate
active
06229727
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to computer memories and more particularly to a method and apparatus for accommodating different memory configurations within a single multi-pin DIMM socket.
BACKGROUND OF THE INVENTION
Most microprocessor-based computing devices, used to execute a variety of application programs, include a microprocessor and a separate memory (RAM) each residing in a separate package or “circuit chip” on a printed circuit motherboard. The memory stores and retrieves data in a matrix according to a predefined addressing scheme. The microprocessor typically accesses data stored in multi-bit words at various locations within the memory over corresponding multi-bit address lines. According to the addresses provided to the memory, data words are output over an output bus that is, in turn, interconnected with the microprocessor and with a variety of other data handling devices both on the board and remote from the board.
To facilitate assembly, maintenance and replacement of computing components, each circuit chip package is applied to a multi-pin socket that is, in turn, permanently mounted on the motherboard. One popular socket arrangement for accommodating random access memories is the so-called dual in-line memory module (DIMM) socket. This socket generally defines one hundred individual pin connections in a preferred arrangement. Each pin is at a standardized location on the socket and is designated by a standard “pin number.” In general, the microprocessor, DIMM socket and other circuit components are connected by a series of discrete lines that are permanently placed on the motherboard, and that, consequently, are not reconfigurable. In other words, a particular pin of the microprocessor is permanently tied to a particular pin on the DIMM socket. This limits the ability of the dim socket to support memory devices other than those specifically designed to interface with certain interconnections or pins. However, the physical geometry of the dim socket is such that it can support several different types and sizes of memories. For example, the socket can accommodate the popular extended data out random access memory (EDO) available in a plurality of memory densities from 1 megabytes up to 32 or 64 megabytes. The addressing scheme for each of such devices is often slightly different. In particular, each different size, and array configuration (number of rows versus columns) requires more, less or different address pins to be employed. This means, that simply attaching different-sized memory into the same DIMM socket on a motherboard will not guarantee that the desired microprocessor address pins are connected with the proper addressing functions of the microprocessor. In particular, each EDO device may contain a different number of row versus column address pins. Some common configurations/sizes are detailed in the following table, which assumes one bank of memory per socket:
TOTAL
MEMORY
DEVICES
SIZE (× 32)
EMPLOYED
REFRESH
ROWS
COLUMNS
1 Mbyte
256K × 4
512
9
9
1 MByte
256K × 16
512
9
9
1 MByte
256K × 16
1K
10
8
2 Mbyte
512K × 8
1K
10
9
4 Mbyte
1 Mbyte × 16
1K
10
10
4 Mbyte
1 Mbyte × 4
1K
10
10
8 Mbyte
2 Mbyte × 8
2K
11
10
16 Mbyte
4 Mbyte × 4
4K
12
10
16 MByte
4 Mbyte × 4
2K
11
11
16 Mbyte
4 Mbyte × 16
4K
12
10
32 Mbyte
8 Mbyte × 8
8K
13
10
Accordingly, it is an object of this invention to provide an apparatus and method for supporting a variety of different memory configurations and sizes within a single socket. The underlying architecture should be simple to configure for the different size memories. It should not require excessive amounts of additional software or hardware to enable the configuration.
SUMMARY OF THE INVENTION
This invention overcomes the disadvantage of the prior art by providing a method and apparatus for supporting different sizes and configurations of random access memory in a single DIMM socket without altering the underlying physical connectivity between sockets/circuit components. In general, the address lines of the microprocessor are interconnected through a multiplexer and buffer arrangement. The multiplexer divides the connected address lines into two groups. The two groups of address bits, so divided, are selectively routed to predetermined pin connections of a DIMM socket that interconnect with predetermined address lines of the resident random access memory. Me address bits are transmitted to the pin connections during each of the row address cycle and the column address cycle of the memory. The interconnections between the multiplexer and the random access memory are arranged so that a variety of standardized address pin configurations are supported by the same socket. This, in part, results from standardized locations for address bits for a variety of memory devices, varying primarily in the presence or absence of higher order address bits for rows and/or columns. The architecture of this invention enables the microprocessor to be programmed to operate with a given size of memory, and for the appropriate connections to the desired memory address lines to be already present.
In this manner, the user can select an address configuration that is appropriate to a particular predetermined memory device without altering the physical connections between the microprocessor and the DIMM socket The addressing scheme provided by the microprocessor is constant, and the multiplexer to produces the desired addressing scheme at the DIMM socket to accommodate a given memory device. The actual address configuration of the memory device is “transparent” to the microprocessor.
In a preferred embodiment, the random access memory can comprise an extended data out dynamic random access memory (EDO) having a desired size and “width.” The microprocessor can comprise an MPC 860 PowerQuicc™ available from Motorola. Multiple sockets can be arranged in parallel in the form of discrete memory banks, having data and address busses arranged in parallel. Control of read/write, column and row addressing functions can also be arranged in parallel. In a typical arrangement, row address strobe (RAS) functions are used to select between particular memory banks, enabling each selected bank at a predetermined time.
REFERENCES:
patent: 5176525 (1993-01-01), Nierescher et al.
patent: 5257166 (1993-10-01), Marui et al.
patent: 5287455 (1994-02-01), Rosenthal
patent: 5495435 (1996-02-01), Sugahara
patent: 5671149 (1997-09-01), Brown
patent: 5797031 (1998-08-01), Shapiro et al.
patent: 5982655 (1999-11-01), Doyle
Motorola, MC 68360 Quad Integrated Communications Controller User's Manual Rev:.1, 9-48.
Cesari and McKenna LLP
Cisco Technology Inc.
Thai Tuan V.
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