Method and apparatus for streamlined testing of electrical circu

Details Method and apparatus for streamlined testing of electrical circu Method and apparatus for streamlined testing of electrical circu

1995-02-21

1996-06-11

Voeltz, Emanuel T.

Excavating

G01R 313183

Patent

active

055263658

ABSTRACT:
A serial scan test architecture can perform testing of an electrical circuit without cycling through multiple data register shift operations required by conventional test architectures by permitting test signals to be transferred bidirectionally between serial scanning circuitry and functional circuitry while serial data is being transferred in a continuous serial data stream between the test controller and the serial scanning circuitry.

REFERENCES:
patent: 4698588 (1987-10-01), Hwang et al.
patent: 4710933 (1987-12-01), Powell et al.
patent: 5130647 (1992-07-01), Sakashita et al.
IEEE Standard Test Access Port and Boundary-Scan Architecture, Feb. 1990, pp. 1-3, 1-5, 5-5.
Mourad, Samiha, "Sequential Circuit Testing," COMPCOM Spring '90 IEEE Computer Society Int'l Conference, 1990, pp. 449-454.
Lee Whetsel, "An IEEE 1149.1 Based Logic/Signature Analyzer in a Chip", International Test Conference, Oct. 26-30, 1991.
Sridhar Narayanan, Charles Njinda and Melvin Breuer, "Optimal Sequencing of Scan Registers", IEEE, 1992, International Test Conference 1992, Paper 15.2, pp. 293-302.

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