Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-08-14
2002-06-18
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S106000, C438S109000, C438S014000, C438S015000
Reexamination Certificate
active
06406940
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the manufacturing of printed circuit boards or the like, containing integrated circuits (ICs) and other semiconductor devices. More particularly, the present invention pertains to techniques and apparatus for stacking integrated circuits.
BACKGROUND OF THE INVENTION
Modern electronic circuits are generally constructed on printed circuit boards, utilizing integrated circuits and other electrical components mounted on the boards and appropriately interconnected. With such integrated circuits comprising one or more semiconductor devices, such electronic circuitry provides the advantages of relatively sturdy and reliable construction, reduced lengths of component interconnections with consequent reduced impedance and electrical signal traces, and enhanced miniaturization. These features of modern circuitry find particular application to the field of implantable medical devices, such as heart pacemakers and defibrillators. For example, smaller implant devices require smaller incisions, and provide less bulk for the patients receiving the implants to endure. Also, the patients may receive greater benefit from an implant device that has enhanced capabilities made possible by an increase in the extent of the circuitry contained therein, particularly if the size of the circuit board is not increased.
A conventional printed circuit board provides a substrate made of plastic, ceramic, or other suitable material, and may be constructed of multiple layers of electrically conductive sheets mutually separated by electrically insulating layers. Conducting paths are selectively constructed in the conductive sheets, including traces located along the planes of the sheets, and conducting channels are formed passing through holes, or vias, in insulating layers to interconnect traces or terminals on different conducting layers. A variety of components, including semiconductor integrated circuits, or chips, may be mounted on the top planar surface of such a circuit board, for example, and electrically connected to the circuit by connection to pads, or terminals.
In the quest for miniaturization of printed circuit board components, particularly for such applications as implantable medical devices, it has been found that a chip can be stacked on another chip that is already mounted on a printed circuit board. The second, or upper, chip is positioned on the first, or lower, chip so as to not cover the connection pads on the first chip, or to be so close as to interfere with the making of connections to those pads. Then both chips may be wire-bonded, or otherwise connected, into the circuitry on the printed circuit board.
While electronic circuitry comprising integrated circuits and other semiconductor devices in the form of chips, or dies, may provide relatively sturdy and reliable components, the actual manufacture of such circuitry requires considerable care and delicacy of operation due, for example, to the fragile nature of such devices. In the process of stacking one chip on another, for example, the upper chip must be properly aligned with the lower chip; otherwise, if the upper chip is deposited even slightly rotated or laterally shifted out of alignment, it may interfere with the making of electrical connections to the pads on the lower chip. Further, such a misaligned upper chip may be damaged in the process of connecting the lower chip. Still further, either or both of the chips may be damaged if the upper chip is brought into contact with the lower chip in a tilted orientation, or with too much force, resulting in a collision between the two chips. Placing the second chip on the first chip manually, or by lowering the second chip using a mechanical device, can result in misalignment between the two chips, or a collision between them with resultant chip damage.
It has been found that chip damage can be avoided by positioning the second chip a short distance above the first chip, and dropping the second chip into place. Thus, the second chip falls under the force of its own weight, which is very small, being on the order of 0.013 g, and no damaging collision takes place. A vacuum tool may be used to pick up the second chip and position that chip over the first chip. Release of the vacuum allows the second chip to fall into place on the first chip. However, to maintain both the rotational alignment and the level orientation of the second chip as it falls through the air to contact the lower chip, the distance over which the second chip is dropped must be minimized, and the second chip must be released to fall without deflection. At the same time, however, the gap between the two chips before the upper chip is released to fall must be sufficient to avoid the possibility of an inadvertent collision between the two chips while the upper chip is still being held.
It would be desirable and advantageous to provide a technique for stacking one chip on top of another that avoids the possibility of damage to either of the two chips, and which enables the upper chip to be placed in proper alignment on top of the lower chip. Further, it would be desirable and advantageous to provide a technique for minimizing the distance the second chip is dropped while also reducing the possibility of a collision between the two chips while the upper chip is still being held. The present invention provides such technique, and avoids the problems discussed above.
SUMMARY OF THE INVENTION
The present invention provides a method for stacking semiconductor chips, and includes the steps of providing a vertical reference level, positioning a first chip below the reference level, determining the vertical distance between the reference level and a top level of the first chip, engaging and supporting a second chip, manipulating the second chip over the first chip, aligned with the first chip, with the vertical distance between the reference level and the level of the bottom of the second chip, compared to the vertical distance between the reference level and the top level of the first chip, being such that the vertical distance between the level of the bottom of the second chip and the top level of the first chip is no greater than a selected distance, and releasing the second chip to fall into a stacked configuration on the first chip.
The top level of the first chip is the level of the top of adhesive positioned on the top surface of the first chip. The step of determining the vertical distance between the reference level and the top level of the first chip includes either (a) the steps of applying adhesive to the top surface of the first chip, and then determining the vertical distance between the reference level and the top level of the first chip, that is, the level of the top of the adhesive, or (b) the steps of determining the vertical distance between the reference level and the top surface of the first chip, and then applying adhesive to the top surface of the first chip to a selected thickness, establishing the top level of the first chip as the level of the top of the adhesive.
The vertical distance between the reference level and the top level of the first chip may be determined by utilizing the angle at which light is reflected, or by utilizing autofocusing, or by utilizing mechanical sensing, for example.
The steps of manipulating the second chip may be performed using a scale fixed relative to the vertical reference level to determine the vertical distance between the vertical reference level and level of the bottom of the second chip.
The steps of engaging, supporting, manipulating, and releasing the second chip may be performed using a vacuum tube on the end of which the second chip is carried, and a scale whereby the vertical position of the second chip, carried by the vacuum tube, relative to the reference level may be determined. Alternatively, the steps of engaging, supporting, manipulating, and releasing the second chip may be performed using a mechanical grasping system.
REFERENCES:
patent: 4654694 (1987-03-01), Val
patent: 5239447 (1993-08-01)
Bowers Charles
Geyer Scott B.
Intermedics Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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