Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
2006-08-22
2006-08-22
Donaghue, Larry D. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C712S231000, C712S215000, C718S102000, C718S104000, C718S106000
Reexamination Certificate
active
07096343
ABSTRACT:
A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very long instruction word architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes instruction packet splitting to recover some efficiency lost with conventional multithreaded architectures. Instruction packet splitting allows an instruction bundle to be partially issued in one cycle, with the remainder of the bundle issued during a subsequent cycle. The allocation hardware assigns as many instructions from each packet as will fit on the available functional units, rather than allocating all instructions in an instruction packet at one time. Those instructions that cannot be allocated to a functional unit are retained in a ready-to-run register. On subsequent cycles, instruction packets in which all instructions have been issued to functional units are updated from their thread's instruction stream, while instruction packets with instructions that have been held are retained. The functional unit allocation logic can then assign instructions from the newly-loaded instruction packets as well as instructions that were not issued from the retained instruction packets.
REFERENCES:
patent: 5404469 (1995-04-01), Chung et al.
patent: 5574939 (1996-11-01), Keckler et al.
patent: 5805852 (1998-09-01), Nakanishi
patent: 5890009 (1999-03-01), Luick et al.
patent: 6170051 (2001-01-01), Dowling
Kim et al. Multithreaded VLIW Processor Architecture for HDTV, 2000.
Berenbaum Alan David
Heintze Nevin
Jeremiassen Tor E.
Kaxiras Stefanos
Agere Systems Inc.
Donaghue Larry D.
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