Patent
1997-01-28
1999-11-23
Beausoliel, Jr., Robert W.
G06F 1120
Patent
active
059915188
ABSTRACT:
A split brain avoidance protocol to determine the group of processors that will survive a complete partitioning (disconnection) in the inter-processor communications paths connecting processors in a multi-processor system. Processors embodying the invention detect that the set of processors with which they can communicate has changed. They then choose either to halt or to continue operations, guided by the goal of minimizing the possibility that multiple disconnected groups of processors continue to operate as independent systems, each group having determined (incorrectly) that the processors of the other groups have failed.
REFERENCES:
patent: 4590554 (1986-05-01), Glazer et al.
patent: 4868818 (1989-09-01), Madan et al.
patent: 4879716 (1989-11-01), McNally et al.
patent: 4939752 (1990-07-01), Literati et al.
patent: 5367697 (1994-11-01), Barlow et al.
patent: 5452441 (1995-09-01), Espsito et al.
PCT International Search Report for PCT/US98/01379 dated May 20,1998.
Basavaiah Murali
Jardine Robert L
Krishnakumar Karoor S
Beausoliel, Jr. Robert W.
Elisca Pierre E.
Tandem Computers Incorporated
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