Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Reexamination Certificate
2000-03-07
2003-08-19
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
C712S219000, C712S213000, C712S242000, C712S243000, C712S245000
Reexamination Certificate
active
06609191
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to the field of microprocessor instruction translation, and more particularly to translating and pairing of micro instructions for parallel execution.
2. Description of the Related Art
A present day pipeline microprocessor has a single path, or channel, or pipeline, that is divided into stages that perform specific tasks. Each of the specific tasks are part of an overall operation that is directed by a programmed instruction, or macro instruction. Each of the macro instructions in a software application program, such as a spreadsheet program, is executed in sequence by the microprocessor. As a macro instruction enters the first stage of the pipeline, certain tasks are accomplished. The instruction is then passed to subsequent stages for accomplishment of subsequent tasks. Following completion of a final task, the instruction completes execution and exits the pipeline. Execution of macro instructions by a pipeline microprocessor is very much analogous to the manufacture of items on an assembly line.
One of the first stages in the pipeline is the translation stage. In the translation stage, macro instructions, such as Intel x86 architecture instructions, are translated into one or more micro instructions. Examples of x86 macro instruction are the MOV (move data), MUL (multiply), PADD (MMX packed add) and PMUL (MMX packed multiply) instructions. The micro instructions generated when macro is are translated are typically simpler instructions than the macro instructions. The micro instructions are passed down the pipeline and executed by the various stages of the pipeline. When completion of the last micro instruction making up the macro instruction occurs, execution of the macro instruction is complete.
There is an incessant demand for improvement in the performance of microprocessors. That is, there is a constant demand for an increase in the number of instructions per second executed by microprocessors. One means of improving performance is for a microprocessor to execute instructions in parallel, where possible, rather than sequentially. That is, parallel execution occurs where a microprocessor executes two or more instructions concurrently, rather than in sequence. However, parallel instruction execution within microprocessors may present certain challenges.
In particular, instructions that have a resource conflict may not be executed in parallel, but must be executed sequentially. For example, if two instructions require the same resource for execution, such as an adder, the instructions may not be executed in parallel if there is only one adder, but must instead be executed sequentially. However, if two adders are present within the microprocessor, the possibility exists that the two instructions may be executed in parallel rather than sequentially.
Furthermore, even if multiple execution resources are present, the instructions may not be executed in parallel if the instructions have an operand dependency. For example, if instruction A requires as an operand a result from instruction B, then the two instructions may not be executed in parallel. The instructions may not be executed in parallel because the instruction B must be executed first and produce its result in order for the instruction A to use the result of the second instruction as an operand.
As may be readily observed, if micro instructions are executed in parallel within the microprocessor pipeline, on the whole, the number of macro instructions that will be executed per second will tend to increase.
One means of executing micro instructions in parallel in a single pipeline of a microprocessor is to pair two micro instructions and send them down the pipeline together for parallel execution by execution stages of the single pipeline. U.S. patent application Ser. No. 09/313,907 filed May 14, 1999 entitled PAIRING OF MICRO INSTRUCTIONS IN THE INSTRUCTION QUEUE, now U.S. Pat. No. 6,330,657, having the same assignee, and hereby incorporated by reference, describes a micro instruction pairing method. The application describes a method in which a translator receives macro instructions and generates micro instructions that are stored into an instruction queue. Subsequent to the generation of the micro instructions and their storage in the instruction queue, pairing logic scans the micro instructions in the instruction queue to determine whether two of the micro instructions may be paired for parallel execution. If the pairing logic finds two pairable micro instructions in the instruction queue and they do not have a resource conflict or operand dependency, the pairing logic pairs the micro instructions and stores them in an instruction register. The instruction register sends the paired micro instructions down to subsequent stages in the pipeline for parallel execution.
This technique is particularly useful when the downstream stages of the pipeline are not waiting to receive micro instructions to execute. That is, the translator has an entire clock cycle to translate macro instructions into micro instructions. Likewise, the pairing logic has an entire clock cycle to scan the instruction queue and pair micro instructions.
However, when the downstream stages of the pipeline are waiting to receive micro instructions to execute, i.e., the instruction register is empty, it is disadvantageous to store the micro instructions in the instruction queue in hopes of later pairing micro instructions. In this situation, the translator provides the next micro instruction directly to the instruction register so that the downstream stages of the pipeline have an instruction to execute. However, it should be recognized that a potential missed opportunity to pair micro instructions is lost since pairing is performed only on micro instructions already stored in the instruction queue.
Thus, what is needed is a translator that is capable of translating macro instructions into micro instructions and pairing the micro instructions for provision to an instruction register when necessary in a single clock cycle. However, translation of x86 instructions into micro instructions may take a substantial portion of the clock cycle, leaving little time for a determination of whether the prospectively pairable micro instructions have a resource conflict or operand dependency. This is largely due to the nature of x86 macro instructions.
In particular, x86 macro instructions are variable in length. For example, some x86 macro instructions are a single byte long, whereas other x86 macro instructions are multiple bytes long. Thus, as the translator translates macro instructions into micro instructions it must examine a fetched stream of bytes to determine the length of each instruction and frame the stream of bytes into distinct x86 macro instructions. Once the macro instructions are framed, their instruction type (such as integer, MMX or floating point) must be determined, various operands must be parsed, etc., and finally the constituent micro instructions must be generated. All of these operations combine to consume a significant portion of the microprocessor clock cycle used to perform translation leaving little time to perform the pairing of micro instructions, in particular the necessary checks for resource conflicts and operand dependencies.
Therefore, what is needed is an apparatus that allows a translator time to determine if two micro instructions are pairable, in addition to the normal time required to generate the micro instructions, without incurring an additional clock cycle to pair the micro instructions.
SUMMARY
To address the above-detailed deficiencies, it is an object of the present invention to provide a microprocessor that speculatively pairs micro instructions and selectively splits the paired micro instructions if a resource conflict or operand dependency is detected. Accordingly, in attainment of the aforementioned object, it is a feature of the present invention to provide a microprocessor for speculatively pairing micro instructions for parallel
Hooker Rodney E.
Jain Dinesh K.
Parks Terry
Davis E. Alan
Huffman James W.
IP-First LLC
Pan Daniel H.
LandOfFree
Method and apparatus for speculative microinstruction pairing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for speculative microinstruction pairing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for speculative microinstruction pairing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3124328