Patent
1994-07-12
1996-07-09
Robertson, David L.
395473, 395477, G06F 1314
Patent
active
055353630
ABSTRACT:
A method and apparatus that allows a snoop phase of a memory transaction to be shortened or skipped is described. During processing of a present memory transaction, the ownership of a system bus during previous memory transactions, as well as the data addresses requested for those transactions, are tracked. If the ownership and requested address of the present transaction match those from the previous transaction, a Next Address signal is provided that allows another transaction to proceed before the snoop phase of the present transaction is completed. In alternate embodiments, the ownership and addresses for multiple transactions are tracked and compared with the ownership and addresses of the present transaction. If a match occurs, the Next Address signal is asserted.
REFERENCES:
patent: 5325503 (1994-06-01), Stevens et al.
patent: 5404489 (1995-04-01), Woods et al.
patent: 5408627 (1995-04-01), Stirk et al.
Intel Corporation
Robertson David L.
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