Method and apparatus for single phase clock distribution with mi

Details Method and apparatus for single phase clock distribution with mi Method and apparatus for single phase clock distribution with mi

1997-08-18

1999-06-08

Butler, Dennis M.

395558, G06F 104

Patent

active

059110635

ABSTRACT:
A method and apparatus are provided for generating and distributing a single phase clock in a processor design. A single phase clock signal is generated and applied to a metal grid structure. The metal grid structure is used to distribute the single phase clock signal across an integrated circuit chip. Local clock buffers are used to generate a local clock copy and a local clock complement of the single phase clock signal. Testing is provided with scannable latches by enabling a multiplexer in the latches to select between functional data, scan data, and a reload of latch data. Pipelined globally routed multiplexer scan and hold signals control scan and hold functional modes of the multiplexer. A latch hold function allows the single phase global clock signal to appear functionally as multiple clock frequencies.

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K. Klein, D. Schmunkamp and U. Weiss, IBM Technical Disclosure Bulletin, "Clock Distribution Tree for Minimal Clock Skew," vol. 36, No. 05, May 1993, pp. 307-308.

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