Method and apparatus for simultaneously minimizing storage and m

Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements

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395401, 345185, G06F 1200

Patent

active

054540763

ABSTRACT:
An image is written to a data frame buffer for display by a monitor. The image includes a repeated pattern. The present invention uses a repeated pattern cache which is not large enough to simultaneously contain an entire repeated pattern. When writing a pixel of the image, a horizontal pattern offset and a vertical pattern offset for a destination location of the pixel are determined. If a scan line for the repeated pattern which corresponds to the vertical pattern offset does not reside in the repeated pattern cache, the scan line for the repeated pattern which corresponds to the vertical pattern offset is fetched into the repeated pattern cache. When the scan line for the repeated pattern which corresponds to the vertical pattern offset resides in the repeated pattern cache, the pixel is accessed at a location in the repeated pattern cache at a location which corresponds to the horizontal pattern offset. The accessed pixel is written to the buffer.

REFERENCES:
patent: 5131080 (1992-07-01), Fredrickson et al.
Richard F. Ferraro, Programmer's Guide to the EGA and VGA Cards, Addison-Wesley Publishing Company, Inc., 1990, pp. 182-227.
James D. Foley, et al., Computer Graphics Principles and Practice, Addison-Wesley Publishing Company, Inc., 1987, pp. 164-187.

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