Computer graphics processing and selective visual display system – Display driving control circuitry – Physically integral with display elements
Reexamination Certificate
1998-01-05
2001-01-09
Peikari, B. James (Department: 2752)
Computer graphics processing and selective visual display system
Display driving control circuitry
Physically integral with display elements
C345S111000, C382S203000, C382S173000, C382S260000, C382S305000, C382S243000
Reexamination Certificate
active
06172670
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a memory accessing method for providing access to a frame buffer by pixel interleaving and a data processing apparatus for performing pre-set data processing by accessing a frame buffer by the memory accessing method. The memory accessing method and the data processing apparatus can be utilized in a video game machine or a graphic computer system such as video equipment employing a computer.
2. Related Art
In a picture generating apparatus for generating data of a picture outputted to and displayed on a display device, such as output picture data for a television receiver, a monitor receiver or a cathode ray tube (CRT) display device, that may be used in a video game device or a graphics computer system, a dedicated drawing device is provided between a central processing unit (CPU) and a frame buffer to permit high-speed processing.
That is, in such a picture generating apparatus, the CPU generating a picture performs geometry processing, such as coordinate transformation, clipping or light source calculations, instead of directly accessing the frame buffer. The CPU then defines a three-dimensional model as a combination of basic unit figures, such as triangular or quadrangular figures, formulates a drawing command for drawing a three-dimensional picture, and sends the drawing command to the drawing device.
For example, if, in the above-described picture generating apparatus, a three-dimensional object is represented, the object is resolved into a plurality of polygons, and a drawing command associated with each polygon is transmitted from the CPU to the drawing device. The drawing device interprets the drawing command sent from the CPU and executes rendering processing of computing colors and Z-values of all pixels making up the polygon from Z-values for writing pixel data in a frame buffer for drawing a picture.
The Z-values represent color data and depth of all pixels making up a polygon. That is, the Z-value provides information representing distance along a depth from a viewing point.
The above-described picture generating device also has the function of executing pixel interleaving by writing a plurality of pixel data at a time to a corresponding plurality of addresses of a frame buffer, which serves as an accessing unit, and the picture generating device is configured to access the frame buffer by this function.
However, with the pixel interleaving performed by the above picture generating device, a plurality of simultaneously accessible addresses are available in each accessing unit.
Therefore, if a picture represented by the plurality of simultaneously accessible addresses and a picture drawn on the frame buffer, that is the shape formed by the data actually desired to be accessed, are not coincident with each other, the number of times that the frame buffer must be accessed is undesirably increased.
Moreover, if the number of times that the frame buffer must be accessed is increased, the performance of the data processing carried out by the picture generating device decreases.
In view of the above-depicted state of the art, the present invention has the following objects.
Specifically, it is an object of the present invention to provide a memory accessing method in which interleaving patterns of simultaneously accessible addresses are selected to allow the memory to be accessed with a minimum number of accessing operations increasing the memory accessing efficiency.
It is another object of the present invention to provide a data processing apparatus in which simultaneously accessible addresses are selected to allow the memory to be accessed with a minimum number of accessing operations for raising the data processing efficiency.
SUMMARY OF THE INVENTION
In one aspect, the present invention provides a memory accessing method for simultaneously accessing a plurality of addresses of a memory wherein addresses to be accessed simultaneously are determined depending on a shape in the memory of data desired to be accessed.
In the memory accessing method according to the present invention, the data may be picture data.
In the memory accessing method according to the present invention, the addresses to be accessed may be determined depending on the aspect ratio of the shape.
In the memory accessing method according to the present invention, the addresses to be accessed may be selected from a plurality of patterns.
In another aspect, the present invention provides a data processing apparatus for performing pre-set data processing by simultaneously accessing a plurality of addresses in a memory including accessing means for simultaneously accessing a plurality of addresses in the memory, and control means for determining the addresses simultaneously accessed by the accessing means depending on the shape of input data.
In the data processing apparatus of the present invention, the data is picture data.
In the data processing apparatus of the present invention, the control means determines the simultaneously accessed addresses depending on the aspect ratio of the shape of the input data.
In the data processing apparatus of the present invention, the control means selects the accessed addresses from a plurality of patterns.
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Hiroi Toshiyuki
Oka Masaaki
Fulwider Patton Lee & Utecht LLP
Peikari B. James
Sony Computer Entertainment Inc.
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