Data processing: structural design – modeling – simulation – and em – Modeling by mathematical expression
Reexamination Certificate
2000-12-21
2004-11-30
Phan, Thai (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Modeling by mathematical expression
C703S003000, C716S030000
Reexamination Certificate
active
06826517
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, a semiconductor device, a semiconductor simulation method and a simulator, and more particularly to improve performance of lumped elements of devices and fabrication yield in scaled large scale integration (LSI), in conjunction with a computer aided design (CAD) tool.
2. Description of the Prior Art
Semiconductor design and fabrication have a wide variety of issues, relating to LSI fabrication, process design, system design, device design, and so on. Problems underlying the current process/device/system design phase are described.
First, a historical overview and the current status of the semiconductor industry and LSI device research and development phase are described. The semiconductor industry has continued to prosper as the result of continuous improvement of productivity and creative research throughout its history. It is believed that these trends will continue into the foreseeable future. It is instructive to quantitatively sketch the time evolution of high-tech consumer electronics in terms of product size. In the past decade, for example, the overall volume of mobile communications and personal computers has been reduced by an order of magnitude or more, with corresponding weight savings being realized. The number of transistors per microprocessor chip and per memory chip as a function of year is shown in FIG.
1
. The time-dependent increase in the number of transistors on microprocessor and memory integrated circuit chips is shown in a logarithmic scale.
Regarding device size in the chips, the gate length of the devices and the isolation area size have been reduced as the number of transistors has increased. Roughly speaking, a typical design rule of a first phase of 256M DRAM (Dynamic Random Access Memory) has been around 0.25 microns. As a common language in the LSI industry and academia, the phrase ‘design rule’ is used as technology generation. ‘LSI’ is an integrated science and technology across large areas as its word literally says; circuit technology, device technology, mathematics, chemistry, physics, electrical engineering, computer simulation, and so on. So, a typical design ‘rule’ as technology generation specification is a very useful and convenient index in order to share and own a common meaning among engineers.
FIG. 2
shows the typical technology parameters as a function of LSI generation. A design rule is shown in terms of DRAM capacity, year of the first production and so on. From
FIG. 2
, it is understood that the continual drive towards smaller feature size in device fabrication results in tighter design criteria and increased complexity of equipment used in semiconductor processing.
Basic research and developments have already started intensively for 0.13 microns or more scaled-down device/process design phase in universities, many LSI companies, and institutions all over the world.
FIG. 3
show a cross section image of typical recent devices, which is appeared in a reference, J. G. Ryan, R. M. Geffken, N. R. Poulin, and J. R. Paraszczak,
IBM J. Res and Develop
. 39, 371 (1995). Abbreviations of M1 to M5 are metal layers. At the bottom layer of
FIG. 3
, are MOS devices. There is a need to contact and interconnect (M1 to M4) among all of the semiconductor electrodes, i.e., source, drain, and gate, to other components and devices on the chip. The highest level (M5) is composed for bus-bars that carry current to chip contact pads.
FIG. 4
shows the number of metal layers as a function of technology generation. The signal delay among a large number of devices is minimized, so eventually a multi-layered structure of metallization was used. It can be seen from
FIG. 4
that with reducing design rule, more metal layers are needed. The increase of the integration density, while maintaining the same RC signal delay leads to a strong increase of the number of the metal layers. This trend is mitigated by introducing new materials. Historically, SiO
2
has been well adopted for passivation films and interlayer dielectric films, and aluminum has also been well accepted as an interconnect metal. In
FIG. 4
, some of the improvements are also presented; such as introducing Cu/SiO
2
, and some low epsilon materials. As overviewed above, the semiconductor industry has continued to prosper as the result of continuous improvement of productivity and creative research throughout its history. Also intensive research and developments have already started for 0.17 micron or more scaled-down device/process design phase.
As background, the LSI fabrication process is described. The LSI fabrication process has been composed basically of diffusion, silicidation, oxidation, chemical vapor deposition (CVD), ion implantation, etching and so-forth. These processes have been done repeatedly on semiconductor silicon substrates.
Before this LSI device fabrication, photomasks are made based on desired design rules. The design rules provide a necessary communication link between circuit designer and process engineer during the manufacturing phase. The main objective associated with layout rules is to obtain a circuit with optimum yield (functional circuit versus nonfunctional circuits) in as small an area as possible without compromising the reliability of the circuit. In general, design rules have represented the best possible compromise between performance and yield. The more conservative the rules are, the more likely it is that the circuit will function. However, the more aggressive the rules have been, the greater the probability of improvements in circuit performance. This improvement has been at the expense of yield. Based on these huge efforts, LSI has been continuously prosperous up to now.
Computer simulation tools for reducing time-around-time in trial and error phase are described.
FIG. 5
shows an overview of the process flow of the simulator SUPREM (Stanford University Program for IC Process Engineering Models) which is one of the most famous and widely used simulators. Oxidation, diffusion, ion implantation, etching processes which are mentioned above, have been implemented in computer simulation programs based on chemical/physical models as subroutines. Most of the trial and error in research and development phase are done in computer programs. One can estimate and predict easily impurity profiles and final device structure in advance of actual fabrication. Once some impurity profiles are obtained in the device, then, device characteristics can also be calculated. FIG.
6
(
a
) shows a three-dimensional graph of the potential plotted from a conventional device simulation solution based on estimated impurity profiles. Moreover, FIG.
6
(
b
) shows a graph of subthreshold current in the simulated MOSFET (metal oxide semiconductor field effect transistor). So, eventually, the device characteristic for individual unit device can be estimated from an input process sequence. These CAD tools such as SUPREM to have now been indispensable in LSI fabrication lines.
FIG. 7
is a flow chart showing a typical conventional design process phase for an analog integrated circuit for telecommunications. Here, the ‘simulation’ is also seen. The task of designing an analog or digital integrated circuit includes many steps.
FIG. 7
illustrates the general approach to the design of an integrated circuit. The major steps in the conventional design process are:
1) definition,
2) synthesis or implementation,
3) simulation or modeling,
4) geometrical description,
5) simulation including the geometrical parasitics,
6) fabrication, and
7) testing and verification.
The circuit designer is responsible for all of these steps except fabrication. The first major task is to define and synthesize the design. This step is crucial since it determines the performance capability of the design. When this task is completed, the designer must be able to confirm the design before it is fabricated. This leads to the second major task—using simulation methods to predict
Gray Cary Ware & Freidenrich LLP
Kabushiki Kaisha Toshiba
Phan Thai
LandOfFree
Method and apparatus for simulating manufacturing,... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for simulating manufacturing,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for simulating manufacturing,... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3318394