Method and apparatus for simulating an electrical circuit design

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

G06F 1560

Patent

active

060885238

ABSTRACT:
A method and apparatus for making electrical circuits having RLCG lines is disclosed. The method depicts a circuit element taper of a selected element type as dependent upon an accumulated circuit element quantity. The method matches projections of the circuit element taper with projections of an approximate taper. The approximate taper depends upon the accumulated circuit element quantity. At least one reduced quantity for circuit element quantities of the selected element type is obtained on the computer. The one reduced quantity can be arranged in a reduced RLCG line having approximately the same performance as the RLCG line. The present invention should be particularly useful in verifying timing specifications and during the making of integrated circuits.

REFERENCES:
patent: 5313398 (1994-05-01), Rohrer et al.
patent: 5379231 (1995-01-01), Pillage et al.
patent: 5581202 (1996-12-01), Yano et al.
patent: 5696693 (1997-12-01), Aubel et al.
Bracken et al,"Interconnect Simulation with Asymptotic Waveform Evaluation", 1992, IEEE Circuit Systems-I: Fundamental Theory and Applications, v39, n11, p. 869.
Dahlquist et al, Numerical Methods, 1974, Prentice Hall, Sections 5.8.3-5.8.4.
Elmore, "The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers", 1948, Journal of Applied Physics, v19, p. 55.
Golub et al, Matrix Computations, Second Edition, 1989, Johns Hopkins University Press, pp. 476-481.
Gupta et al, "Domain Characterization of Transmission Line Models and Analyses", 1996, IEEE Computer Aided Design of Integrated Circuits and Systems, v15, n2, p. 184.
Horowitz, "Timing Models for MOS Circuits", 1983, Ph.D. Dissertation, Stanford Electronics Laboratories, Stanford University, Technical Report No. SEL83-003.
Hyatt, Engineering Electromagnetics, Third Edition, 1974, McGraw Hill, pp. 408-413.
Kahng et al, "Efficient Analyses and Models of VLSI and MCM Interconnects", submitted to IEEE VLSI Systems.
Kerns, "Stable and Efficient Reduction of Substrate Model Networks Using Congruence Transforms", 1995 IEEE/ACM International Conference on Computer-Aided Design, IEEE Computer Society Press, p. 207.
Liao et al, "Capturing Time-of-Flight Delay for Transient Analysis Based on Scattering Parameter Macromedel", 1994, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, p. 412.
McCormick, Modeling and Simulation of VLSI Interconnections with Moments, 1989, Ph.D. Dissertation, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology.
O'Brien et al. Efficient On-Chip Delay Estimation for Leaky Models of Multiple-Source Nets, 1990, IEEE Custom Integrated Circuits Conference, 9.6.1.
Pillage et al, "Asymptotic Waveform Evaluation for Timing Analysis", 1990, IEEE Computer Aided Design, v9, n4, p. 352.
Protonotarios et al, "Theory of Non-Uniform RC Lines Part I: Analytic Properties and Realizability Conditions in the Frequency Domain", 1967, IEEE Circuit Theory, v14, n1, p. 2.
Ratzlaff et al, "RICE: Rapid Interconnect Circuit Evaluator", 1991, 28th ACM/IEEE Design Automation Conference, Paper 33.1, p. 555.
Silveira et al, "Efficient Reduced-Order Modeling of Frequency Dependent Coupling Inductance associated with 3-D Interconnect Structures", 1995, 32nd Design Automation Conference, p. 376.
Stoer et al, Introduction to Numerical Analysis, 1980, Springer-Verlag, pp. 142-158.
Tang et al, "Analysis of High-Speed VLSI Interconnects Using the Asymptotic Waveform Evaluation Technique", 1992, IEEE Computer Aided Design, v11, n3, p. 341.
Rao, "Delay Analysis of the Distributed RC Line", 1995, 32nd Design Automation Conference.
Feldman et al, "Efficient Linear Circuit Analysis by Pade Approximation via the Lanczos Process", 1995, IEEE Computer-Aided Design of Integrated Circuits and Systems, v14, n5, p. 639.
Nabors et al, "A Gaussian-Quadrature Based Algorithm for RLC-line to RLC-line Reduction", Submitted to 1996 International Conference on Computer-Aided Design.
Nabors et al, "Lumped Interconnect Models Via Gaussian Quadrature", Submitted to the 1997 Design Automation Conference.
Borchers et al, "Reduction Parasiter RC-Netzwerke in Hochsintegrierten Schaltungen", 1993, Sixth EIS Workshop.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for simulating an electrical circuit design does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for simulating an electrical circuit design, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for simulating an electrical circuit design will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-550699

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.