Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2005-05-24
2005-05-24
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S215000, C712S214000, C712S206000, C710S052000, C710S054000
Reexamination Certificate
active
06898692
ABSTRACT:
A method of processing data relating to graphical primitives to be displayed on a display device using region-based SIMD multiprocessor architecture, has the shading and blending operations deferred until rasterization of the available graphical primitive data is completed. For example, the method may comprise the steps of: a) defining a data queue having a predetermined number of locations therein; b) receiving fragment information belonging to an image to be displayed by the pixel; c) determining whether the fragment information belongs to an opaque image or to a blended image; d) if the fragment information relates to a blended image, storing the fragment information on the next available location in the queue; e) if the fragment information relates to an opaque image, clearing the locations of the queue and storing the fragment information in the first location in the queue; f) repeating steps b) to e) for new fragment information until fragment information is stored in all the locations in the data queue or until no further fragment information is available; and g) processing in turn fragment information stored in the locations of the queue to produce respective pixel display values.
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Cameron Ken
O'Dea Eamon
ClearSpeed Technology plc
Peikari B. James
Potomac Patent Group PLLC
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