Static information storage and retrieval – Addressing – Sync/clocking
Patent
1997-03-12
1999-08-24
Nelms, David
Static information storage and retrieval
Addressing
Sync/clocking
365241, 365194, 36518517, 36518524, G11C 800
Patent
active
059432918
ABSTRACT:
A transition detection circuit includes a low-to-high detector and a high-to-low detector. Each of the detectors includes a normally closed switch that directly transmits an input signal and a delay block that transmits the input signal to control input of the switch after a delay. The delayed input signal opens the switch to block further transmission of the signal and closes a second switch to supply a high voltage in place of the input signal. The transition detector thus provides a short pulse in response to signal transitions with very little delay. To balance a response of the low-to-high detector and the high-to-low detector, the output of the low-to-high detector, which is the slower detector, is applied to the faster input of an output NOR gate. The difference in response time of the NOR gate inputs offsets the difference in response time of the transition detectors.
REFERENCES:
patent: 5224010 (1993-06-01), Tran et al.
patent: 5313435 (1994-05-01), Kim et al.
patent: 5319607 (1994-06-01), Fujii et al.
patent: 5625604 (1997-04-01), Kim et al.
Le Thong
Micro)n Technology, Inc.
Nelms David
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