Electrical pulse counters – pulse dividers – or shift registers: c – Shift register
Reexamination Certificate
2000-05-15
2002-09-10
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Shift register
C377S069000, C377S075000
Reexamination Certificate
active
06449328
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for shifting data from registers.
2. Description of the Related Art
A shifter circuit is used to shift a plurality of data bytes to another register where further computations may be performed. Prior art shifters typically utilize a barrel shifter to allow a plurality of bytes to be shifted to a fixed number of bytes. Certain data processing operations further require byte reordering. The reordering is typically performed by a separate multiplexer circuit.
To shift data, such as bytes, from N registers to M output bytes, an M N:1 multiplexors may be used. For instance, if there are sixteen one byte registers and data is shifted to select four bytes as output, then four 16:1 multiplexors may be used to select data from the sixteen registers and shift to four outputs. However, the larger the multiplexor, the more space and logical units the multiplexor requires to implement.
Thus, there is a need in the art for an improved shifter architecture for a shifter that utilizes fewer logical units for the multiplexor than that described above.
SUMMARY OF THE PREFERRED EMBODIMENTS
To overcome the limitations in the prior art described above, preferred embodiments disclose a method and apparatus for shifting data from registers. Bits from N registers are shifted as input to a first set of M multiplexors. Control signals are sent into each of the first set of M multiplexors to select bits inputted from one of the registers. The selected bits are outputted to each of a second set of M multiplexors. Control signals are then sent into each of the second set of M multiplexors to select bits inputted from each of the first set of multiplexors.
In further embodiments, a counter generates a control word. The control word is used to determine the control signals sent to each of the first and second sets of M multiplexors.
In still further embodiments, bits from the control word are used to determine bits to output as control signals to each of the first set of multiplexors. Bits are used from the control word as control signals to each of the second set of multiplexors.
Preferred embodiments provide a technique for implementing a barrel shifter data from registers while rotating through the registers in a manner that efficiently utilizes multiplexor circuits to reduce the number of multiplexor logical units needed to implement the barrel shifter.
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International Business Machines - Corporation
Konrad Raynes Victor & Mann
Victor David W.
Wambach Margaret R.
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