Method and apparatus for sheet resistance measurement of a wafer

Details Method and apparatus for sheet resistance measurement of a wafer Method and apparatus for sheet resistance measurement of a wafer

1988-09-14

1989-09-19

Eisenzopf, Reinhard J.

Electricity: measuring and testing

Conductor identification or location

Inaccessible

324 62, 295691, 118712, G01R 2708, H01L 2100

Patent

active

048684902

ABSTRACT:
The sheet resistance of an integrated circuit wafer (W) may be measured during an integrated circuit fabrication process step. A chamber (26) has disposed therein a plurality of probes (40) each having a conductive tip (84) for abutting the work surface at a respective preselected location thereon. A current source (52, 114) is connected by at least two conductors (118, 112) between at least two of the tips (110, 116). A voltmeter (50) is connected between at least two of the tips (120, 126) by further conductors (122, 124). The voltmeter (50) is read out while the process step is being performed, and the voltage is converted to a sheet resistance according to the preselected electrical configuration of the circuit and a predetermined formula.

REFERENCES:
patent: 3660250 (1972-05-01), Duffy et al.
patent: 4335350 (1982-06-01), Chen
patent: 4536051 (1985-08-01), Smith et al.
patent: 4543576 (1985-09-01), Hieber et al.
patent: 4726961 (1988-02-01), Diem et al.
patent: 4780086 (1988-10-01), Jenner et al.
Holmwood, Sheet Resistance Monitor for Deposition of Thin Films, 8-1966, IBM Tech. Dis. Bulletin, Vol. 9, No. 3, pp. 247-248.

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