Boots – shoes – and leggings
Patent
1990-06-29
1993-11-16
Dixon, Joseph L.
Boots, shoes, and leggings
364DIG1, G06F 1314
Patent
active
052631443
ABSTRACT:
A cache coherency scheme in a multiprocessor computer system allows data sharing between caches at a fast rate. A new cache coherency state is introduced which allows a processor pair to more effectively share data and eliminate bus transfers thereby improving system throughput. The transfer of data is accomplished by the returning a portion of a preselected data block pursuant to either a read or a read for ownership request by a first one of the processors of the processor pair by the second processor of the processor pair. The ownership of the portion of the preselected data block is shared by the processor pair. Both processors set an indicator to denote that the preselected data block is an incomplete data block.
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"Cache Memories" by Alan Jay Smith, Computing Surveys, vol. 14, No. 3, Sep. 1982.
De Rosa John
Ramanujan Raj
Zurawski John H.
Digital Equipment Corporation
Dixon Joseph L.
Elmore Reba I.
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