Method and apparatus for sharing a signal line between agents

Details Method and apparatus for sharing a signal line between agents Method and apparatus for sharing a signal line between agents

1997-03-27

2000-08-29

Auve, Glenn A.

39520062, 39520067, G06F 1300

Patent

active

061120162

ABSTRACT:
Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented. Specific support falls into three areas: the extension of snooping to support multiple caches, the support of shared data between the two processors, and the provision of a processor and upgrade arbitration protocol that permits dual processors to share a single grant signal line.

REFERENCES:
patent: 4719569 (1988-01-01), Ludemann et al.
patent: 5201051 (1993-04-01), Koide
patent: 5230043 (1993-07-01), Ichihashi et al.
patent: 5291529 (1994-03-01), Crook et al.
patent: 5408636 (1995-04-01), Santeler et al.
patent: 5418914 (1995-05-01), Heil et al.
patent: 5524237 (1996-06-01), Bestler et al.
patent: 5551005 (1996-08-01), Sarangdhar et al.
patent: 5568617 (1996-10-01), Kametani
patent: 5572703 (1996-11-01), MacWilliams et al.
patent: 5764935 (1998-06-01), Bechtolsheim et al.
PCI Local Bus Specification, Revision 2.0; PCI Special Interest Group; Hillsboro, OR; Apr. 1993.
Intel, :Pentium Processor User's Manual Volume 2: 82496 Cache Controller and 82491 SRAM Data book, 1994, P5-114 to 5-115.

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