Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-03-15
2004-03-02
Marcelo, Melvin (Department: 2663)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S429000, C370S470000
Reexamination Certificate
active
06700894
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to packet switching systems and methods, and more specifically to a shared buffer architecture for packet switching devices.
2. Description of the Prior Art:
A wide variety of architectures may be employed in the design of packet switching devices and packet switching fabrics. Examples of common packet switching architectures include cross-bar architectures, ring topology architectures, and shared buffer architectures. Each of the different types of architectures provides different advantages for use in different types of networks. Traditionally, the shared buffer switching architecture has been used in networks supporting the propagation of fixed length packets, commonly referred to as cells. Packet switching devices designed in accordance with conventional shared buffer architectures provide peak bandwidth performance when designed specifically to switch cells of a predetermined length as further explained below. For example, shared buffer switching devices used in asynchronous transfer mode (ATM) networks are typically designed to provide optimal utilization of memory space of the shared buffer, as well as optimal bandwidth performance in an ATM network wherein the cell size is fixed at 53 bytes. Although conventional shared buffer packet switching devices may be used for switching packets of varying lengths, the bandwidth performance of shared buffer switching devices suffers when switching variable length packets because a large amount of memory space of the shared buffer is wasted as further explained below.
FIG. 1
shows a schematic block diagram of a conventional shared buffer packet switching device at
10
which is commonly employed in networks supporting the propagation of cells (e.g., an ATM network). The device
10
includes: a plurality of N serial receive ports
12
designated RX
0
, RX
1
, RX
2
, . . . , RX
N−
providing serial reception of bits of cells received via associated links (not shown) of a network; and a plurality of N serial transmission ports
14
designated TX
1
, TX
2
, TX
3
, . . . TX
N−
providing serial transmission of bits of cells via associated links of the network. The serial receive ports RX
0
, RX
1
, RX
2
, . . . , RX
N−
and associated ones of the serial transmission ports TX
1
, TX
2
, TX
3
, . . . TX
N−
are typically formed by bi-directional network ports communicatively coupled with associated network links.
The shared buffer switching device
10
further includes: a source managing unit
18
having a plurality of N ports
20
each for receiving cells from an associated one of the receive ports
12
via an associated one of a plurality of N receive buffers
22
; a shared buffer
26
having a port
28
communicatively coupled with the source managing unit
18
via a bus
30
as further explained below; and a destination managing unit
34
having a plurality of N ports
36
each being communicatively coupled with an associated one of the transmission ports
14
of the device via an associated one of a plurality of N transmit buffer queues
38
. Typically, the shared buffer
26
is implemented using static random access memory (SRAM) technology, and is addressable by the source managing unit
18
and destination managing unit
34
via memory address values as further explained below.
The source managing unit
18
includes: a packet forwarding module
50
for receiving cells from each of the receive buffers
22
via a bus
54
, and a port
56
as further explained below; and a buffer managing unit
60
having a port
62
communicatively coupled with each of the receive buffers
22
via the bus
54
, and with port
52
of the packet forwarding module
50
via the bus
54
, a port
64
communicatively coupled with port
28
of the shared buffer
26
via the memory bus
30
, a port
66
communicatively coupled with port
56
of the packet forwarding module, and a port
68
communicatively coupled with port
42
of the destination managing unit
34
. Operation of the device
10
is further explained below.
FIG. 2
shows a generalized table diagram illustrating a memory space at
72
of the shared buffer
26
(FIG.
1
). The memory space
72
includes a plurality of word locations
74
of the shared buffer memory space, each word location being addressable via a corresponding memory address value
76
, and having a word storage space
78
for storing an associated word of data having a word length of B bits. The shared buffer
26
(
FIG. 1
) is said to have a “width” of B bits, and a “height” equal to the total number of addressable word locations
74
. As further explained below, because hardware requirements dictate that the shared buffer
26
have a fixed word length, or width, a bandwidth problem arises in using a shared buffer memory for switching variable length packets.
Referring back to
FIG. 1
, in operation of the switching device
10
, cells are received serially via associated network links at each one of the receive ports
12
and temporarily stored in the associated receive buffers
22
which are used in converting the received cells from the serial data format to a parallel data format for storage in the shared buffer. The packet forwarding module
50
is responsive to address values (e.g., MAC address values) carried by the received cells, and operative to determine destination port information associated with each of the received cells by reading a cell forwarding table (not shown), the destination port information indicating a destination one of the transmission ports
14
associated with the received cell. The packet forwarding module
50
provides the destination port information associated with each one of the received cells to port
66
of the buffer managing unit
60
via its port
56
.
The buffer managing unit
60
is operative to determine a memory address value
76
(
FIG. 2
) associated with each of the received cells, the associated memory address values indicating word locations
74
(
FIG. 2
) for storing the received cells. The buffer managing unit
60
is then operative to store (write) the received cells in the associated word locations
74
(FIG.
2
), and is also operative to provide the destination information and the memory address values associated with of the each cells to port
42
of the destination managing unit
34
which uses the information to perform output queuing operations.
The destination managing unit
34
receives and temporarily stores the destination information and memory address values associated with each of the cells. The destination managing unit
34
includes output queuing logic (not shown) for arbitrating between requests on behalf of received cells for access to associated destination ones of the transmit buffer queues
38
. After resolving requests and selecting a received cell for access to an associated one of the transmit buffer queues
38
, the destination managing unit
34
reads the selected cell from the associated word location
74
(
FIG. 2
) of the shared buffer
26
using the associated memory address value, and forwards the cell to the associated one of the transmit buffer queues
38
.
Note that one cycle is required to access, that is read or write, a word of data to the shared buffer
26
, and therefore the shared buffer
26
may serve one of the receive ports
12
or one of the transmission ports
14
at a time for writing (storing) and reading (retrieving) cells. The switching device
10
is generally synchronous in that cells are received serially by the receive buffers
22
, converted from serial to parallel format, and stored in the shared buffer.
The buffer manager
60
accesses word locations
74
(
FIG. 2
) of the shared buffer
26
in accordance with allocated times slots associated with each of the receive ports
12
, and with each of the transmission ports
14
. Typically, the access operations are synchronized in accordance with a write cycle in which the buffer manager
60
stores a cell received by each of the N receive ports
12
during
Broadcom Corporation
Lee Andy
Marcelo Melvin
Squire Sanders & Dempsey L.L.P.
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