Method and apparatus for setting a bit-serial filter to an all-z

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36472416, G06F 1710

Patent

active

057544557

ABSTRACT:
Bit-serial digital filters use numerous flip-flops, which must be reset to a known, all-zero state for testing and start-up purposes. A method for setting a bit-serial digital filter to an all-zero state uses non-resettable flip-flops, which eliminates the increased gate count and current drain overhead of resettable flip-flops. A bit-serial digital filter is constructed using non-resettable flip-flops such as simple non-resettable D flip-flops. When a reset signal is initiated, a reset controller (350) sends an all-zero signal to reset gates (301, 321) positioned at the input to the digital filter and in each feedback loop or unit-delay path. Meanwhile, a bit-serial controller (250) cycles through its control signals to emulate the operation of the bit-serial filter. In two word cycles, each flip-flop in the digital filter will be set to a known, all-zero state, and the all-zero signal is removed to allow normal operation of the filter.

REFERENCES:
patent: 3714402 (1973-01-01), Baumwolspiner
patent: 4285047 (1981-08-01), Ohnishi
patent: 5034909 (1991-07-01), Hartley
patent: 5204831 (1993-04-01), Gazsi et al.
patent: 5335194 (1994-08-01), Clayton et al.

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