Method and apparatus for servicing simultaneous I/O trap and deb

Boots – shoes – and leggings

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395737, 364230, G06F 946

Patent

active

057457700

ABSTRACT:
A microprocessor includes the capability to service at least one debug exception and an I/O trap generated during execution of a single instruction. After executing each instruction, the microprocessor determines whether a debug exception and an I/O trap occurred. If at least one debug exception and an I/O trap exist, then the microprocessor determines an active status for the debug exception. The microprocessor stores the contents of internal registers, constituting a state of the microprocessor, to memory, and latches a breakpoint status for the debug exception in a public debug status register. The breakpoint status is preserved by copying the breakpoint status to a private debug status register. The microprocessor services the I/O trap by executing a SMM handler, an upon returning from the SMM handler, the state of the microprocessor is restored. If the I/O trap serviced requires instruction restart, then the state of the microprocessor is adjusted to re-execute the instruction. The microprocessor copies the breakpoint status, stored in the private debug status register, to the public debug status register when the I/O trap does not require instruction restart. The debug exception is subsequently serviced by executing an INT1 handler.

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Intel486.TM. SX Microprocessor Data Book; a publication of Intel Corporation, Aug., 1992.

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