Method and apparatus for serially programming an on-chip EPROM i

Details Method and apparatus for serially programming an on-chip EPROM i Method and apparatus for serially programming an on-chip EPROM i

1991-06-21

1993-10-19

Fears, Terrell W.

Static information storage and retrieval

Addressing

Sync/clocking

36518903, G11C 1300

Patent

active

052552446

ABSTRACT:
Apparatus for serially programming a microcontroller's on-chip EPROM includes mode decode logic that responds to operating mode input signals by generating corresponding operating mode signals, including an EPROM mode signal. An upper byte address shift register serially receives a most significant address portion of an EPROM address in response to a shift clock signal and provides the most significant address portion as an upper byte parallel output. A lower byte address shift register serially receives a least significant address portion of the EPROM address in response to the shift clock and provides the least significant address portion as a lower byte parallel output. A memory address register loads the upper and lower byte parallel outputs from the upper and lower byte address shift registers, respectively, and provides an EPROM address output in response to a load signal. An EPROM memory element responds to the EPROM address by providing access to a storage element specified by the EPROM address.

REFERENCES:
patent: 5079742 (1992-01-01), Simpson

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