Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1998-02-02
2001-04-10
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S052000, C327S057000
Reexamination Certificate
active
06215331
ABSTRACT:
BACKGROUND OF THE INVENTION
Analog comparators are fundamental building blocks of analog-to-digital converters (ADC's). Analog comparators often consist of two circuit blocks: a differential amplifier that amplifies the difference between a reference voltage and an analog input voltage, and a sense amplifier/regenerative latch (sense amp/latch). The sense amp/latch senses the amplified difference between the reference voltage and the analog input voltage and converts that difference into a digital 1 or a 0, based on whether the amplified voltage difference is positive or negative.
FIG. 1A
illustrates an example of a prior art comparator
100
. Comparator
100
includes differential amplifier
102
and sense amp/latch
104
. An input voltage V
in
and a reference voltage V
ref
are compared by comparator
100
, and complementary outputs Q and {overscore (Q)} are produced to indicate which input (V
in
or V
ref
) is higher.
A commonly used topology for a sense amp/latch
104
is shown in FIG.
1
B. In
FIG. 1B
, transistors M
IP
and M
IN
comprise an input differential pair that accepts the positive (V
P
) and negative (V
N
) voltage outputs, respectively, from the amplifier
102
shown in FIG.
1
A. Transistors M
1
through M
4
comprise a cross-coupled inverter pair that creates regenerative feedback in a well-known manner when device MS is opened and device MP is closed. The circuit of FIG.
1
B accepts a differential input and produces a differential output. Optimally M
IP
, M
3
and M
1
should be matched in terms of their physical and electrical characteristics to their counterparts on the other half of the circuit (M
IN
, M
4
and M
2
).
The conventional sense amp/latch
104
has two phases of operation: a combined reset/sense phase (a negative feedback mode) and a latching phase (a positive feedback mode). A representative scheme for driving a comparator that uses the sense amp/regenerative latch of
FIG. 1B
is shown in FIG.
2
. Throughout this application and the accompanying drawing figures, the terms Q and {overscore (Q)}, QR and {overscore (QR)}, LATCH and {overscore (LATCH)}, SENSE and {overscore (SENSE)}, and the like are digital complements of each other, e.g., when LATCH is a digital
1
, {overscore (LATCH)} is a digital 0 (and vice versa).
Referring to
FIGS. 1B and 2
, during the combined reset/sense phase {overscore (LATCH)} is high, device MS is closed, and device MP is opened; as a result, transistors M
3
and M
4
are electrically isolated from the power supply (V
DD
) and device MS brings nodes N
1
and N
2
substantially close to their common-mode voltage level (which is equal to the average gate-source voltages of M
1
and M
2
) from their previous voltages (e.g., previous logic states) quickly. The combination of MS, M
1
and M
2
forms a differential load to the differential pair M
IP
and M
IN
, and the sense amp/latch
104
behaves like a differential amplifier in this mode. Thus, given enough time, nodes N
2
and N
1
develop a voltage between them of A* (V
P
-V
N
) where A is the gain of sense amp/latch
104
when it is behaving like a differential amplifier.
FIG. 3
shows an equivalent circuit to the circuit of
FIG. 1B
when it is operating in the latching phase. During the latching phase, {overscore (LATCH)} is low, device MP is closed, and device MS is opened. As a consequence, the sources of devices M
3
and M
4
are electrically connected to the power supply (V
DD
) via device MP and the combination of transistors M
1
through M
4
operate as two back-to-back connected inverters and enable positive regenerative feedback (see FIG.
1
B). The positive feedback causes the voltages on nodes N
1
and N
2
to change rapidly in opposite directions until the voltage on node N
1
gets close to the supply rail (V
DD
) and the voltage on node N
2
gets close to the ground rail, or vice versa, depending on the initial voltages on node N
1
and node N
2
.
In the circuit of
FIG. 1B
, the single device MS affects both the reset and sensing operation of the combined reset/sense phase, and the optimization of device MS is important for a fast reset and latch operation. However, the sizing of device MS is determined by two conflicting requirements: the conductance of device MS needs to be large enough to reset the circuit quickly, so that previous latched decisions will have no influence on the current decision (no memory), yet small enough such that large voltage gain from the input differential signal (V
P
-V
N
) to the differential signal of nodes N
2
and N
1
(V
N2
-V
N1
) occurs. Larger gain during the sensing operation provides a larger output to the latch; this results in faster latching and a smaller required input voltage to overcome the latch output offset. This is accomplished by selecting a size and control terminal voltage for device MS such that the conductance imposed by MS barely overcomes the negative conductance imposed by devices M
1
and M
2
, so that the small signal conductance (inverse of the load resistance) formed substantially by the combination of M
1
, M
2
, and MS is small and positive. The two conflicting requirements (fast reset and large gain) limit the speed with which reset and latching can be performed for the circuit shown in FIG.
1
B.
SUMMARY OF THE INVENTION
The present invention relates to the design of a high speed sense amp/latch. More particularly, the present invention separates the reset/sense phase of the sense amp/latch into two separately controllable operations. By separating the reset/sense phase into two separately controllable operations, the parameters associated with optimization (speed and/or completeness of reset vs. larger gain during sensing) are substantially independent of each other and therefore do not conflict with each other.
The separation of the reset/sense phase into two separately controllable operations is accomplished by setting a load impedance of the sense amp/latch to a first level during a reset phase, to a second level during a sensing phase, and to a third level during a latching phase.
In a first embodiment, a load impedance is controlled by applying a three-level voltage to the control terminal of a transistor (e.g. the gate of an MOS device), setting the load impedance in each of the three phases of operation (reset, sense, and latch) to three different levels, respectively.
In a preferred embodiment, two separate devices are used for controlling a load impedance of a sense amp/latch during the three phases of operation.
REFERENCES:
patent: 5032744 (1991-07-01), Liu
patent: 5055720 (1991-10-01), Tiede
patent: 5699305 (1997-12-01), Kawashima
patent: 5854562 (1998-12-01), Toyoshima et al.
Page 761 ofAnalysis and Design of Analog Integrated Circuits, Second Edition, P.R. Gray and R.G. Meyer (John Wiley & Sons 1984).
Mastrocola Angelo R.
Setty Palaksha A.
Agere Systems Inc.
Lam Tuan T.
Synnestvedt & Lechner LLP
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