Method and apparatus for sensing defects in integrated circuit e

Details Method and apparatus for sensing defects in integrated circuit e Method and apparatus for sensing defects in integrated circuit e

1988-09-09

1990-06-26

Smith, Jerry

Excavating

371 214, 371 151, G06F 1100

Patent

active

049378260

ABSTRACT:
An apparatus for testing for faults in an integrated circuit is attached to sense lines which are coupled to output nodes of logic gates of a test structure within an integrated circuit, such as a "Cross-Check" test structure built into an integrate circuit apparatus. A related method provide precharging of the sense lines to a known signal level prior to using the sense lines to sense the signal level at a test point. The apparatus combined with sense amplifiers or comparators attached to the sense lines may adjust detection levels of the comparators synchronously to test for either an output "one" minimum level (VOH) or output "zero" maximum level (VOL) to test for other classes of faults. The apparatus attached to the sense lines may inject charge into an output node of a logic gate at preselected times in a test sequence to modify the signal level at that output node to test for faults. A method according to the invention includes path sensitization whereby test patterns can be reduced to Boolean expressions.

REFERENCES:
patent: 4592026 (1986-05-01), Matsukawa
patent: 4672610 (1987-01-01), Salick
patent: 4739250 (1988-04-01), Tanizawa
patent: 4749947 (1988-06-01), Gheewala
"Fault Coverage Requirement in Production Testing of LSI Circuits" by V. D. Agrawal et al., pp. 57-61, IEEE Journal of Solid-State Circuits, vol. SC-17, No. 1, Feb. 1982.
Gopal Gupta and N. K. Jha, "A Universal Test Set for CMOS Circuits", IEEE Transactions on Computer-Aided Design, pp. 590-597, vol. 7, No. 5, May 1988.
R. Rajsuman et al., "Testing of Complex Gates", Electronics Letters, Jul. 30, 1987, vol. 23, pp. 813-814.
"Built-In Self-Test Structures", and Built-In Self-Test Techniques by Edward J. McCluskey, Stanford University, Apr. 1985, IEEE Design & Test, pp. 21-36.
"Test Length in a Self-Testing Environment" by T. W. Williams, pp. 59-63, IEEE Design & Test.

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