Data processing: structural design – modeling – simulation – and em – Electrical analog simulator – Of electrical device or system
Reexamination Certificate
1999-09-14
2001-10-16
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Electrical analog simulator
Of electrical device or system
C703S005000, C703S013000
Reexamination Certificate
active
06304834
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a simulation technique for various semiconductor devices, such as integrated circuits (LSIs, VLSIs, ULSIs or GSIs), high frequency transistors, power semiconductor devices, light emitters, photodetectors, and the like, and a manufacturing method using it. More particularly, the present invention relates to a device simulation method, an apparatus for the device simulation (a device simulator), a physically readable recording medium on which a device simulation program is stored, and a manufacturing method for the semiconductor device using them.
2. Description of the Related Art
In the manufacturing of a complex advanced semiconductor device, it is not desirable to test the behaviors of the semiconductor devices, after fabricating actual samples and measuring the characteristics of the actual devices, since there may be a fear of waste of enormous time and cost. For this reason, the following methodology is being preferably employed, in these days. That is, before starting the fabrication process of the semiconductor devices such as LSIs, which may have very small feature sizes, the highly integrated structures or the highly packed structures, the physical or electrical characteristics of the semiconductor devices scheduled to be manufactured are simulated on the basis of numerical calculation by a computer system. In the numerical calculation, the geometrical structures, physical principles or the boundary conditions are supposed to be substantially similar to those of the actual semiconductor device. Then, the evaluations are performed on the simulated results of the semiconductor device to thereby check the virtual device behaviors. And finally, the actual manufacturing process is executed, if the affirmative results are obtained.
However, if some calculation errors are included in the result of the simulation, a problem is naturally brought about in the semiconductor device manufacturing process based upon it. For example, if the failures are observed in the characteristics and the like after the completion of the prototype through a long complex fabrication process needing several weeks or more, the design must be again reviewed, and the long complex fabrication process must be again repeated, which causes a waste of time and a running cost to be uselessly spent. In this way, the improvement of the accuracy of the simulation is very important since it directly contributes to the reduction of a manufacturing period of the semiconductor device. Originally, it is impossible to recover a time lost by failure of the design. Especially, the speed of the developments of the semiconductor device having higher performances are competed among many manufacturing firms in the semiconductor industry. So, the reduction of the period from the design stage to the product stage is extremely important.
In a device simulation to obtain the device behavior of the semiconductor device, input data such as the geometrical structures, the impurity profiles, terminal voltages and the like are prepared at first, and are then input to the device simulator. Then, the device simulator obtains the solutions of the Poisson's equation, the electron current continuity equation and the hole current continuity equation which are “the basic equations” for prescribing the electrical characteristics of the semiconductor devices by numerical calculation. As a result, the device simulator outputs the device behaviors of the semiconductor device.
The basic equations required to obtain the electrical characteristics of the semiconductor device are simultaneous differential equations of the potential distribution and the carrier concentration (actually, the electron concentration n and the hole concentration p), as represented by the following equations (1) to (3):
∇·
D=q
(
p−n+N
D
−N
A
) (1)
∂(−
qn
)/∂
t+∇·J
c
=−qU
(2)
∂(
qp
)/∂
t+∇·J
n
=qU
(3)
Here, D is the electric displacement vector, q is the absolute electron charge, N
D
is the donor concentration, N
A
is the acceptor concentration, t is the time, J
e
is the electron current density vector, J
n
is the hole current density vector, and U is the net carrier generation-recombination rate. Moreover, a potential &psgr;, a electron concentration n and a hole concentration p at each point of the semiconductor device are arbitrarily given to the basic equations as “the initial guess”. Then, modification is added until those values satisfy the above-mentioned basic equations, and the solutions are obtained by using the computer system and the like. However, in order to solve the basic equations (1) to (3) by using the computer system, it is necessary to carry out “the discretization” of the carrier current density vector.
As shown in
FIG. 1
, in the device simulation, a finite number of grid points (mesh points) are firstly defined inside and around the semiconductor device targeted by the simulation (referred to as an analysis area). In a case of a two-dimensional space, polygons with each grid point at the vertex are defined (in a case of a three-dimensional space, polyhedrons with each grid point as the vertex are defined). This polygon is referred to as “the grid”. These polygons or polyhedrons cover the analysis area without gap and overlap. Physical parameters are defined associated with the grid points, as necessary. Also, the space within the polygon or the polyhedron, which contains a grid point therein, is referred to as “the control volume”. Namely, each control volume is associated with each grid point. The control volumes also cover the analysis area without gap and overlap. The discretization implies a technique of calculating carrier current density vector flowing out from (or flowing into) the control volume on the basis of the physical parameter at the grid point.
Two prior art techniques are well known with regard to this discretization of the carrier current density vector. One is a technique disclosed in “
Analysis and Simulation of Semiconductor devices
” by Siegfried Selberherr, Springer-Verlag, Wien N.Y., 1984, 6.3
“Finite Elements
”, pp.181-191. Hereafter, this technique is referred to as “the first prior art”. The first prior art employs the Scharfetter-Gummel scheme (usually referred to as “the S-G scheme”), known as a method for calculating the carrier current density flowing on a one-dimensional line. The first prior art applies the S-G scheme to a grid system of a triangle or a quadrangle located on a two-dimensional plane. That is, the first prior art calculates the carrier current density flowing on each line (a side of the triangle or the quadrangle) in the grid system by using the S-G scheme, under the assumption that the carrier current flows only on each line in the grid system. This two-dimensional grid system is similar to a circuit in which conductive lines are linked in the same configuration. The first prior art calculates the current flowing on a conductive line linked between nodes in this circuit. This calculation is as follows.
At first, a current
Sel
I
0,1
flowing out from the control volume corresponding to a grid point I is given by the following equation. Here, definitions of symbols as shown in
FIGS. 2 and 3
are used:
Sel
I
O
,
I
=
∑
j
=
0
N
1
I
IJ
SG
(
4
)
And
SG
I
0,1
is the current flowing on a side IJ having a grid point I and a grid point J, from point I to point J. It is defined by the following equation:
SG
I
0.1
=(
d
IJ
·D
IJ/l
IJ
)(
B
IJ
C
I
−B*
IJ
C
J
) (5)
B
IJ
=B
(
Q&psgr;
IJ
/kT
) (6)
B*
IJ
=B
(−
Q&psgr;
IJ
/kT
) (7)
Here, k is the Boltzmann's constant, T is the temperature, C
I
and C
J
are carrier concentrations at respective grid points I, J. &psgr;
IJ
is the potential difference (&psgr;
IJ
=&psgr;
I
−&psgr;
J
) in the respective grid points I, J. d
IJ
is the dis
Foley & Lardner
Jones Hugh
Kabushiki Kaisha Toshiba
Teska Kevin J.
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