Method and apparatus for semiconductor device optimization using

Details Method and apparatus for semiconductor device optimization using Method and apparatus for semiconductor device optimization using

1996-10-29

1998-08-18

Heckler, Thomas M.

Boots, shoes, and leggings

364490, G06F 1500

Patent

active

057969930

ABSTRACT:
An on-chip optimization circuitry (105) of a semiconductor device (100) provides a delay value to a delay generator (120) indicating an amount to delay an active signal edge. Based on the delay value, a modified device timing is created. Using the modified device timing, a portion of the semiconductor device (130) is tested using on-chip verification circuitry (110) to determine functionality. Based on functionality, a determination is made whether an optimal delay value has been found (550). If an optimal delay value has not been determined, a new delay value is used to produce a new modified device timing (516) and the sequence of testing and determining functionality is repeated until a optimized value has been determined.

REFERENCES:
patent: 4855969 (1989-08-01), Mydill
patent: 5475605 (1995-12-01), Lin
patent: 5572717 (1996-11-01), Pedersen
patent: 5629859 (1997-05-01), Agarwala et al.
patent: 5751593 (1998-05-01), Pullela et al.

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