Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1995-10-31
2000-05-30
Powell, William
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
438725, 216 59, 216 75, 216 71, H01L 21302
Patent
active
060690909
ABSTRACT:
A polysilicon layer is formed on a silicon substrate. A resist film, which has a pattern of remaining portions and opening portions, is formed on the polysilicon layer. The silicon substrate is placed in a reaction chamber, an etch gas is introduced into the reaction chamber, and the introduced gas becomes ionized whereupon dry etching is performed to selectively etch away the polysilicon layer to form projections underneath the remaining portions and recesses underneath the opening portions. By controlling the pressure of the etch gas to fall within a range above 5 millitorr and the flow rate of the etch gas to fall within a range above 100 sccm, both the rate that an etch product is discharged above a recess and the rate that an etch product sticks to a projection sidewall are controlled. Such arrangement not only reduces a critical dimension difference (i.e., a difference in lateral dimension between the bottom of an isolated projection and a corresponding remaining portion of the resist film), but also cancels variations in the critical dimension difference between the isolated projection and the closely spaced projection.
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patent: 5635021 (1997-06-01), Harafuji
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Goudreau George
Matsushita Electric - Industrial Co., Ltd.
Powell William
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