Material or article handling – Device for emptying portable receptacle
Reexamination Certificate
1999-11-12
2001-09-04
Bratlie, Steven A. (Department: 3652)
Material or article handling
Device for emptying portable receptacle
C414S416060, C414S416100, C438S464000, C156S345420
Reexamination Certificate
active
06283693
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to the manufacture of semiconductor devices, and particularly to a method and apparatus for removing semiconductor chips from a diced semiconductor wafer.
A known procedure for fabricating semiconductor chips is to form a plurality of chips integrally within a wafer of semiconductor material and to then dice the wafer, e.g., by sawing, into individual chips. Each chip, or group of chips, is then incorporated within a semiconductor device.
In one known procedure, a completed but still integral wafer is adhered to a thin plastic membrane tautly suspended within an annular frame for fully exposing major surfaces of the membrane. The wafer is then completely sawed through from its upper surface for dicing the wafer into individual chips while not cutting through the underlying membrane.
Prior to or after dicing the membrane, but while the chips are still in precisely ordered array, the individual chips are electrically and mechanically tested and evaluated. The test results are stored, either in a computer or by means of ink markings placed directly on each chip.
The chip assembly is next disposed within a chip transfer station where each good chip is stripped-off the supporting membrane and transferred to a work station where the chip can be, for example, mounted within a semiconductor device being assembled.
In one known chip transfer station, the chip assembly is mounted on an X-Y translating table and horizontally positioned over a pin which is movable along a vertical axis intersecting the plane of the horizontally disposed membrane. The membrane is moved by the translating table for successively disposing each chip on the membrane supported wafer to directly overlie the axis of movement of the push-up pin. When a selected chip is disposed over the push-up pin, the pin is moved upwardly into engagement with the membrane and against the bottom surface of the overlying chip. The engaged chip is raised above the plane of the membrane and against the face of a vacuum pick-up wand of a waiting transfer mechanism positioned above the membrane. The upward movement of the chip is accommodated by a local stretching of the membrane.
The vacuum wand closely overlies the chip surface, and only a relatively short upward lifting of the engaged chip is required to fully contact the raised chip against the wand face. A relatively large vacuum force is provided by the wand, and the chip, fully pressed against the wand face, adheres more firmly to the wand then to the membrane. The pick-up pin is then retracted and the wand is moved upwardly for stripping the attached chip from the membrane. The stretched membrane snaps downwardly into the original membrane plane, and the membrane-stripped chip is then transferred by the transfer mechanism to a further work station where the chip is unloaded from the wand.
The above-described chip transfer process is generally satisfactory except that, as is typically the case, increases in production speed are desired. One technique which has occurred to the inventors herein, for example, is to simultaneously transfer several rather than single chips during each transfer cycle. To this end, an array of push-up pins would be used for simultaneously raising a plurality of selected chips against a corresponding array of vacuum wands disposed closely above the wafer surface. It is desired, however, to transfer only selected chips while leaving non-selected chips firmly in place on the membrane (e.g., for possible future use). The chips are closely spaced together on the membrane and a problem is that, as any single chip is raised by a push-up pin, there is a tendency to also lift immediately adjoining chips mounted on the upwardly stretched membrane. Accordingly, if the chip transfer process comprises, as in the prior art practice, simply raising a selected chip a short distance into the field of attraction of an overlying vacuum wand, the possible slight raising of adjacent chips can likely result in the transfer or dislodgment of such adjacent chips even if non-selected.
A further problem associated with any chip handling process is that the chips tend to be quite small, closely spaced together, and relatively fragile. Thus, some “delicacy” of handling is indicated. In the afore-described prior art process, for example, each engaged chip is raised relatively slowly and only a short distance into contact with the vacuum wand while the chip is still adhered to the membrane. Only after the chip is firmly secured to and supported by the vacuum wand is the chip stripped from the membrane. Accordingly, damage of the delicate chips is avoided.
In accordance with this invention, a somewhat more “radical” approach is used for stripping chips from a membrane and conveying them to a chip transfer mechanism. An advantage, as described hereinafter, is that a higher rate of chip transfers is thus obtained.
SUMMARY OF THE INVENTION
In accordance with this invention, selected ones of a plurality of push-up pins are used for simultaneously engaging and raising a correspondingly selected plurality of chips out of the plane of a diced wafer mounted on a membrane. Each selected pin engages the bottom surface of the membrane, and the membrane portion underlying each selected chip is elastically stretched during the chip lifting process. Different techniques, either alone or in various combinations, are used for ensuring transfer only of selected chips among closely spaced together chips on the membrane.
In a preferred embodiment, each of a plurality of selected chips is simultaneously sharply impacted through the underlying membrane by a respective quite rapidly moving pin for dislodging the chip and projecting it upwardly and against an overlying vacuum wand of an array of wands. The push-up pins are disposed within a vacuum chuck having an apertured flat surface against which the membrane is fly pressed for minimizing upward movements of non-selected chips immediately adjacent to the upwardly stretched portions of the membrane. Additionally, the separation between the various wand faces and the wafer surface is sufficiently large such that, even if some lifting of non-selected chips occurs, the non-selected chips remain sufficiently far from the overlying wands to prevent stripping of such chips.
In accordance with a first embodiment of the invention, the push-up pins are disposed along a straight line and the wafer is periodically indexed for sequentially disposing groups of linearly disposed side-by-side chips over the linear group of pins. Based upon a previous testing and mapping of chips to be transferred, selected ones of the pins are simultaneously driven upwardly for impacting against respective overlying chips for simultaneously projecting the thus selected chips upwardly against respective vacuum wands of a line of wands disposed over the linear group of pins. For structural simplicity, vacuum is applied simultaneously to all the pick-up wands, and selectively in the chip transfer process is achieved solely by selective operation of the push-up pins. For greater selectivity, vacuum is applied only to those wands overlying selected chips to be transferred.
REFERENCES:
patent: 3720309 (1973-03-01), Weir
patent: 4138304 (1979-02-01), Gantley
patent: 4990051 (1991-02-01), Safabakhsh
patent: 5362681 (1994-11-01), Roberts, Jr.
Acello Salvatore
Ansinn Detlev
Bratlie Steven A.
General Semiconductor Inc.
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