Optics: measuring and testing – By alignment in lateral direction – With registration indicia
Reexamination Certificate
2001-06-26
2004-05-11
Lee, Michael G. (Department: 2876)
Optics: measuring and testing
By alignment in lateral direction
With registration indicia
Reexamination Certificate
active
06734971
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to manufacturing processes requiring lithography and more particularly to characterizing and monitoring the inter-field errors of semiconductor wafer stages.
2. Description of the Related Art
Today's lithographic processing requires ever tighter layer-to-layer overlay tolerances to meet device performance requirements. Overlay registration is defined as the translational error that exists between features exposed layer to layer in the vertical fabrication process of semiconductor devices on silicon wafers. Other names for overlay registration include, registration error and pattern placement error, and overlay error. Overlay registration on critical layers can directly impact device performance, yield and repeatability. Increasing device densities, decreasing device feature sizes and greater overall device size conspire to make pattern overlay one of the most important performance issues during the semiconductor manufacturing process. The ability to accurately determine correctable and uncorrectable pattern placement error depends on the fundamental techniques and algorithms used to calculate lens distortion, stage error, and reticle error.
A typical microelectronic device or circuit may consist of 20-30 levels or pattern layers. The placement of pattern features on a given level must match the placement of corresponding features on other levels, i.e. overlap, within an accuracy which is some fraction of the minimum feature size or critical dimension (CD). Overlay error is typically, although not exclusively, measured with an optical overlay metrology tool. See Semiconductor Pattern Overlay, N. Sullivan, SPIE Critical Reviews Vol. CR52, 160:188; Accuracy of Overlay Measurements: Tool and Mark Asymmetry Effects, A. Starikov, et. al., Optical Engineering, 1298:1309, 1992.
Lithographers have crafted a variety of analysis techniques that attempt to separate out systematic process induced overlay error from random process induced error using a variety of statistical methods. See A Computer Aided Engineering Workstation for Registration Control, E. McFadden, C. Ausschnitt, SPIE Vol. 1087, 255:266, 1989; A “Golden Standard” Wafer Design for Optical Stepper Characterization, K. Kenp, C., King, W. W., C. Stager, SPIE Vol. 1464, 260:266, 1991; Matching Performance for Multiple Wafer Steppers Using an Advanced Metrology Procedure, M. Van den Brink, et. al., SPIE Vol. 921, 180:197, 1988; Characterizing Overlay Registration of Concentric 5X and 1X Stepper Exposure Fields Using Interfield Data, F. Goodwin, J. Pellegrini, SPIE Vo. 3050, 407:417, 1997; Super Sparse Overlay Sampling Plans: An Evaluation of Methods and Algorithms for Optimizing Overlay Quality Control and Metrology tool Throughout, J. Pellegrini, SPIE Vol. 3677, 72:82, 36220. The importance of overlay error and its impact to yield can be found elsewhere. See Measuring Fab Overlay Programs, R. Martin, X. Chen, I. Goldberger, SPIE Conference Metrology, Inspection, and Process Control for Microlithography XIII, 64:71, March, 1999; A New Approach to Correlating Overlay and Yield, M. Preil, J. McCormack, SPIE Conference on Metrology, Inspection, and Process Control for Microlithography XIII, 208:216, March, 1999. Lithographers have created statistical computer algorithms (for example, Klass II. See Lens Matching and Distortion testing in a multistepper, sub-micron environment, A. Yost, et al., SPIE Vol. 1087, 233:244, 1989 and Monolith; A Computer Aided Engineering Workstation for Registration Control, supra) that attempt to separate out correctable sources of pattern placement error from non-correctable sources of error. See Analysis of Overlay Distortion Patterns, J. Armitage, J. Kirk, SPIE Vol. 921, 207:221, 1988; Method to Budget and Optimize Total Device Overlay, C. Progler, et al., SPIE Vol. 3679, 193:207, 1999 and U.S. Pat. No. 5,444,538, entitled System and Method for Optimizing the Grid and Intrafield Registration of Wafer Patterns, J. Pellegrini, Aug. 22, 1995. Overall theoretical reviews of overlay modeling can be found in Semiconductor Pattern Overlay, N. Sullivan, SPIE Critical Reviews Vol. CR52, 160:188 and Machine Models and Registration, T. Zavecz, SPIE Critical Reviews Vol. CR52, 134:159.
The effects of overlay error are typically divided into the following two major categories for the purpose of quantifying overlay error and making precise exposure adjustments to correct the problem. The first category, grid or inter-field error, is the positional shift and rotation or yaw of each exposure pattern, exposure field, or simply field, with reference to the nominal center position of the wafer
2001
and
2010
in
FIGS. 20A and 20B
respectively.
Referring to
FIG. 20A
, the intra-field error in field placement on the wafer is shown as a vector offset
2002
for each field. This vector offset is the difference in the placement of the field center from its ideal or nominal position and actual position, and represents one of the components of the inter-field error, that the present invention will determine.
FIG. 20B
shows the other part of intra-field error, which is the yaw or rotational error in the placement of the individual fields, that is also determined by this technique.
Overlay modeling algorithms typically divide grid or inter-field error into sub-categories or components, the first five of which are translation, rotation, magnification or scale, non-orthogonality, and stage distortion. See Matching Performance for Multiple Wafer Steppers Using an Advanced Metrology Procedure, supra. The following discussion is concerned with wafer stage distortion and yaw induced registration or overlay error; these global or inter-field positional errors may be caused by the wafer stage subsystem of the stepper.
The second category, intra-field overlay error, is the positional offset of an individual point inside a projected field referenced to the nominal center of an individual exposure field, as illustrated in FIG.
20
A. Here the term “nominal center” means the exact location of the center of a perfectly aligned exposure field.
FIG. 20A
schematically shows intra-field overlay error as a set of vector displacements within the exposure field, each vector representing the magnitude and direction of the placement error. The following four main components each named for a particular effect are typically used to describe the sources of intra-field error: translation, rotation, scale or magnification, and lens distortion.
Intra-field overlay errors are typically related to lens aberrations and reticle alignment. Separation of the overlay error into inter-field and intra-field components is based on the physically distinguishable sources of these errors, lens aberrations or reticle positioning for intra-field and the wafer stage for inter-field.
It is important for this discussion to realize that most overlay measurements are made on silicon product wafers after each lithographic process, prior to final etch. Product wafers cannot be etched until the alignment attributes or overlay target patterns are properly aligned to the underlying overlay target patterns. There are many types of alignment attributes or overlay target patterns, some of which are shown in FIG.
1
. Others are shown in U.S. Pat. No. 6,079,256 entitled Overlay Alignment Measurement of Wafers, N. Bareket, Jun. 27, 2000 (see FIG. 1
b
); Matching Management of Multiple Wafer Steppers Using a Stable Standard and a Matching Simulator, M. Van den Brink, et al., SPIE Vol. 1087, 218:232, 1989; Automated Electrical Measurements of Registration Errors in Step and Repeat Optical Lithography Systems, T. Hasan, et al., IEEE Transactions on Electron Devices, Vol. ED-27, No. 12, 2304:2312, December 1989; U.S. Pat. No. 5,757,507 entitled Method of Measuring Bias and Edge Overlay Error for Sub 0.5 Micron Ground Rules, C. Ausschnitt et al., May 26, 1998; U.S. Pat. No. 6,143,621 entitled Capacitor Circuit Structure for Determining Overlay Error, K. Tzeng, et al., Nov. 7, 2000. M
Hunter, Jr. Robert
McArthur Bruce
Smith Adlai
Koyama Kumiko C.
Lael Instruments
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