Method and apparatus for self-aligned memory cells and array usi

Details Method and apparatus for self-aligned memory cells and array usi Method and apparatus for self-aligned memory cells and array usi

1998-09-16

1999-12-21

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518501, 36518527, G11C 1604

Patent

active

060058072

ABSTRACT:
A method for fabricating a split gate memory cell using the self-alignment technique to reduce the amount of misalignment is disclosed. The memory cell generally comprises a floating gate for storing a charge, a select gate for selecting one or more memory cell to operate thereon, a control gate, a buried source region and a buried drain region. Due to the structure of the memory cell, there is no read disturbance when reading the memory cell and its low voltage requirement makes it suitable for low voltage applications. When placed in a memory array, each of the memory cells in the array can be individually programmed or read. In performing the erase operation, a column of information is erased.

REFERENCES:
patent: 5705416 (1998-01-01), Kim et al.
patent: 5753953 (1998-05-01), Fukumoto
patent: 5789297 (1998-08-01), Wang et al.

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