Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1998-12-22
2003-01-21
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S017000, C714S037000, C716S030000, C716S030000
Reexamination Certificate
active
06510405
ABSTRACT:
TECHNICAL FIELD
This invention relates to the field of logic simulation of electronic circuits. More specifically, this invention relates to methods and apparatus for selectively displaying signal values generated by a logic simulator.
BACKGROUND OF THE INVENTION
Over the past several decades, computer performance has increased at an exponential rate. A primary reason for this dramatic increase in performance is the rapid advancement of integrated circuit technology. Each generation of integrated circuit technology can typically accommodate four times more circuitry than the previous generation. Because more circuitry can be provided on a single integrated circuit, fewer integrated circuits are required. Besides increasing the performance, circuit integration can reduce the size, power, and cost of such systems.
The design and test of these systems becomes more difficult, time consuming and tedious as system integration increases. One reason for this is that the number of input and/or output pins on an integrated circuit is typically limited, and yet the amount of circuitry on the integrated circuit is dramatically increased. Consequently, modem integrated circuits tend to have an ever increasing number of internal nets that are neither controllable nor observable from the input and/or output pins of the device. This can make testing and debugging such devices difficult.
One approach for increasing the testability of modern integrated circuits is to include built-in-self-test or the like into the design. One built-in-self-test approach involves replacing each of the registers in the design with scan type registers that can operate in both a functional mode (parallel) and in a test mode (serial scan mode). Each of the scan registers is connected to form one or more scan chains. For many built-in-self-test schemes, shadow registers are also provided at the input and output pins. This allows the input and output pins to be both controllable and observable via one or more scan chains.
To test the integrated circuit, the scan registers are put into a test mode, and a test vector is serially scanned into one or more of the scan chains. The scan registers are then put into a functional mode, and clocked once. When the scan registers are clocked, the test vector data passes from the original scan registers, through selected logic, and to receiving scan registers. The scan registers are then put back into the test mode, and the results are scanned out of the circuit and compared to an expected result. This is typically repeated with a number of different test vectors until an acceptable level of fault coverage is obtained.
A limitation of many built-in-self-test schemes is that significant overhead is required. This typically includes replacing each register within the design with a larger and more complex scan register. In addition, many built-in-self-test schemes require that the integrated circuit be in a test mode before a test vector can be scanned into the circuit. Thus, those errors that occur during functional operation are typically not detected and/or analyzed. Software errors or the like, which are traditionally detected and analyzed during functional operation of the device, are therefore not handled well by many built-in-self-test schemes. These limitations detract from the desirability of many built-in-self-test schemes.
To help analyze errors that occur during functional operation of a system, history stacks or the like have been incorporated into circuit designs. A history stack is a collection of “n” registers that store the previous “n” states of one or more nets in the design, where “n” is greater than or equal to one. When an error is detected, the historical data stored in the history stack can then be used to determine the cause of the error. History stacks may be particularly useful because the success of debugging many design problems is dependent on the knowledge of the sequence and type of events that occurred just prior to the unexpected logic behavior or error condition. The historical data stored in the history stacks can often provide this information.
A limitation of using a history stack approach is that significant overhead may be required. A history stack must typically be provided for each net in the design that may be deemed critical during later testing of the circuit. Since it is difficult to predict which nets within the design will be deemed critical for debugging an unexpected problem, circuit designer must typically provide many history stacks throughout the design. These history stacks can represent a significant overhead within the design.
Another limitation of using history stacks is that the proper “critical” nets within the design must be selected during the design phase. This is often problematic because the nets that would be helpful in debugging an unexpected logic behavior cannot be efficiently predicted during the design phase. Thus, it is often difficult to identify the “critical” nets within the design. If the proper critical nets are not identified correctly, historical data relating to a particular error may not be available, making it difficult to debug the error.
Another limitation is that history stacks are typically only useful in detecting errors in hardware that has already been built. It is costly to correct a logic design error after the hardware has been built. To correct just one integrated circuit, for example, at least one new mask must be made, and at least one lot of new wafers must be fabricated using the new mask. This can cost significant amounts of money, and often more importantly, significant amounts of time (e.g. schedule).
To reduce the chance of having a design error, extensive logic simulations are often performed. To perform the logic simulations, the circuit design is often modeled using a high-level behavior language such as the VHSIC (Very High Speed Integrated Circuits) Hardware Description Language (VHDL). Timing information may be included in the model.
Before executing a logic simulation, the circuit designer must typically specify one or more test vectors for forcing the inputs of the design. The circuit designer typically also identifies which of the nets within the design to observe during the simulation. This is typically accomplished by designating selected signals as being listed or traced. When a signal is designated as being traced, for example, the logic simulator may display the logic state of the signal versus time in a wave format. When a signal is designated as being listed, the logic simulator may display the logic state of the signal versus time in a tabular format, wherein each column in the table corresponds to a particular signal, and each row in the table represents a time.
Some logic simulators allow the user to select when to provide an updated listing of the identified signals. For example, some logic simulators have two modes for updating the identified signals. One mode is to list on “interval” and the other mode is to list on “change”. In a list on interval mode, the simulator typically updates the signal values of all listed signals at a specified time interval. The specified time interval is often set to correspond to, for example, the expected clock period of the circuit design. Conversely, the list on change mode typically updates the signal values of all listed signals whenever any of the listed signals changes state. The list on change mode typically provides a longer output than the list on interval mode, at least when timing delays through non-register circuitry is simulated.
Since many circuit designs have a large number of nets, logic simulators typically only store a historical record for those signals that are identified as being listed or traced. Historical data regarding those signals that are not identified as being listed or traced are typically not stored. Since it is difficult to determine in advance which signals will be of interest when debugging an unexpected problem, circuit designers typically designate a large number of signals to be listed or traced
Crompton Seager & Tufte LLC
Johnson Charles A.
Phan Thai
Starr Mark T.
Teska Kevin J.
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