Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
1999-04-02
2002-09-24
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S098000, C345S100000
Reexamination Certificate
active
06456281
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to addressing of pixels arranged in an array format for displaying applications, and more particularly to driving pixel address lines in a video display.
BACKGROUND OF THE INVENTION
Addressable components that can be arranged in rows and columns are commonly found in applications ranging, e.g., from memory to panel video display devices. A matrix display apparatus for displaying video signals commonly comprises a display panel having an array of addressable components arranged in row and column lines of pixels. The two-dimensional row and column lines are usually arranged in a rectangular format. The addressable component is called a picture element, display element, or pixel, and consists of a light sensitive element. The display element may emit, reflect, or transmit light in response to signals addressed into the line. Display elements may be made from different materials and may be constructed in various ways depending on the type and use of the display device. Various types, such as liquid crystal cells, electrochromic cells, plasma cells, fluorescent display tubes, light-emitting diodes (LEDs), and electroluminescence cells have been known. Light modulating materials used to construct display elements have been well known in the industry, and they fundamentally depend on an applied electric field to modulate the amount of light emitted, reflected, or transmitted. Some of the light modulating materials do not exhibit sharp electric field versus light excitation characteristics. Thus, an active device such as a diode or transistor may be used in conjunction with the addressable components to improve the pixel light characteristics. For example, the use of a thin film MOS field effect transistor (TFT) as a switching element is well known to the artisans in the field.
The light output of the picture element may be proportional to the applied addressing signal in the matrix display. In order to address a specific picture element, or pixel, in a matrix display, the pixel must be identified and excited. The excited pixel will emit, reflect, or transmit light accordingly. The pixel in the latter case is being enabled. Within an array of a pixel matrix, each pixel may have a unique address that is specified in terms of row and column location, e.g., the element at row x, and column y, or element (x,y). To excite the pixel (x,y), so that to set it to the “on” status, the pixel (x,y) is enabled by addressing the location (x,y) and exciting the pixel. The pixel may be excited by supplying a voltage above a threshold level to the addressed location.
In one addressing technique, the pixel (x,y) is electrically coupled to a row conductor which intersects with a column conductor. The pixel (x, y) is enabled by addressing the specific row conductor line x and the column conductor line y. Each line is addressed by a driving means, which addresses the line according to an applied signal. The driving means consists of a column driver circuit for each column operable according to the line frequency of an applied video signal for supplying data signals derived therefrom to the column in which the pixel is electrically coupled, a row driver circuit for each row for scanning the row in which the pixel is electrically coupled to, and a control circuit which controls the timing of operation of the driver circuits, which is responsive to an applied video signal.
All pixels arranged in a row line are electrically coupled to a row line and thus to a row driver. Pixels arranged in a column line are electrically coupled to a column line and thus to a column driver. Therefore, M pixels in one row are commonly coupled to a row driver, and each separately coupled to one of M column drivers. Similarly, N pixels in one column are commonly coupled to a column driver, and each separately coupled to one of N row drivers. A matrix display of M×N pixels usually requires M column drivers and N row drivers, or M+N line drivers. Thus, a display with a resolution of 128×1024 pixels consists of 1,310,720 pixels, 1280 columns of pixels and 1024 rows of pixels, and 2304 line drivers. Images are formed by enabling, or disabling, selected pixels in the pixel array usually in sequential manner from left to right and top to bottom.
FIG. 1
depicts a conventional video matrix display device 100 comprising a plurality of pixels P that are arranged along the y-axis in N rows driven by drivers R
N
and along the x-axis in M columns driven by drivers C
M
. Each pixel P has two connecting ports. The first port
122
of the pixel P
1,1
is coupled to the row line
110
a
and the second port
112
of the pixel is coupled to the column line
120
a
. The first port of pixels P
1,1
to P
1,M
are electrically coupled to row
110
a
, while the second ports are separately coupled to the corresponding columns driven by C
1
to C
M
. For example, to enable pixel P
3,4
row line
110
c
is addressed through driver R
3
, and column line
120
d
is simultaneously addressed through driver C
4
. A specific pattern of pixels may be addressed for enabling the pixels by activating a plurality of row and column drivers in a sequential manner. Thus, a large number of drivers are physically needed to construct a matrix display. The number of drivers increases with the increase in the display resolution since larger numbers of rows and columns are needed. A need therefore exists to reduce the number of drivers in a device using addressable components. For high-resolution displays, the cost of a large number of drivers may be significant to the overall cost of the display. The complexity of circuitry components associated with the drivers, such as signal generators, control units, and driver memory also increases with resolution, and further provides a disadvantage in addition to the large number of drivers. Reducing the number of needed drivers in matrix display devices, such as flat panel displays, while achieving or maintaining the same or better image resolution is desirable.
SUMMARY OF THE INVENTION
The problems identified above may be in large part solved by a matrix display method and apparatus that eliminates the large number of row and column line drivers needed to address and selectively enable addressable elements or pixels. To achieve the above advantage, an embodiment of the apparatus may provide a total of only two drivers to drive a M×N display device, such as a flat panel display. A first and a second driver may be used to drive first and second signals at slightly different frequencies (or phase) on a first and a second display conductor. A plurality of pixels may be coupled between the first and second display conductors. The pixels may be addressed according to a pixel location in which the first signal may be approximately in phase with the second signal. The pixel location changes from one pixel to the next at a scan rate proportional to the difference between the first and second signal frequencies. The first and second conductors may contain a plurality of delay elements and tap-off points, wherein each pixel may be coupled between tap-off points on the first and second conductors. A plurality of pixel row and column conductors may be provided, each connected to a different tap-off point of the first and second display conductors.
The row and column conductors may be terminated by their characteristic impedance to prevent any reflection of the traveling signal. Further, the first and the second display conductors may also be terminated by their characteristic impedance to prevent any reflection of the signals traveling on any of the conductors. The periods of the first and second signals may be greater than or approximately equal to a propagation delay of between first and last tap-off points on the first and second conductors, respectively. The pulse width of the first and second signals may be less than or approximately equal to a propagation time of the first and second signal between adjacent tap-off points on the first and second display conductors, res
Conley Rose & Tayon PC
Kowert Robert C.
Piziali Jeff
Shalwala Bipin
Sun Microsystems Inc.
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