Method and apparatus for selecting a mode for updating external

Details Method and apparatus for selecting a mode for updating external Method and apparatus for selecting a mode for updating external

1995-06-01

1997-12-16

Chan, Eddie P.

395470, G06F 1208, G06F 1200

Patent

active

056995482

ABSTRACT:
A processor capable of selecting between a write-back and a write-through mode of operation includes a bus interface unit for transferring information across the external bus. A local cache memory is coupled to the bus interface unit for storing information received from the bus interface unit. The processor also includes a control unit coupled to the cache memory and the bus interface unit. The control unit is operable to restart an interrupted operation from a point of interruption. A storage device coupled to the control unit stores a value corresponding to the point of interruption of the operation.

REFERENCES:
patent: 5025366 (1991-06-01), Baror
patent: 5301298 (1994-04-01), Kagan et al.
patent: 5469555 (1995-11-01), Ghosh et al.
patent: 5471637 (1995-11-01), Pawlowski et al.
patent: 5485592 (1996-01-01), Lau
patent: 5522057 (1996-05-01), Lichy
patent: 5524234 (1996-06-01), Martinez, Jr. et al.

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