Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Converging with plural inputs and single output
Reexamination Certificate
1999-12-30
2001-11-27
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Converging with plural inputs and single output
C327S298000
Reexamination Certificate
active
06323715
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a method and apparatus for switching between clock inputs in a multiplexer without causing a glitch in the output signal.
BACKGROUND OF THE INVENTION
In digital systems that include multiplexers, an output signal is generated from two or more data inputs and one or more select signals. The number of data or clock inputs “n” is less than or equal to 2
k
, where k=the number of select inputs. In a standard multiplexer, once the select input(s) change, the output will begin to reflect the newly selected data input as soon as the select input propagates through the internal logic. If the data input signals being selected are asynchronous to each other, the output pulse width or duration may be narrower than the narrowest data input pulse width. This is called a “glitch”, which can cause substantial problems in digital systems. Any sub-minimum pulse width can violate the timing specification and requirements for other elements in the system causing a variety of operational malfunctions which may range from transitory to more permanent crashes.
In particular, a glitch can be any clock pulse or duration, either high or low, that is shorter in duration than the corresponding pulse of the input clock before or after the clock selection switching. For example, if the system is currently synchronized on a clock of 100 MHz and a switch is made to a clock system of 125 MHz, both clocks having a 50% duty cycle, no clock pulse of duration shorter than four nanoseconds can be generated during selection switching without otherwise resulting in a glitch. Thus a need exists for a method of switching from one clock signal to another clock signal without generating a glitch in the output signal.
SUMMARY OF THE INVENTION
Generally, the present invention relates to digital clocks and to switching between clock signals without generating a glitch at the output. One important advantage of the present invention is the glitchless switching using simple AND/OR gates and logic to form the circuit and to synchronize the clock inputs. Accordingly, a method is described herein that addresses this need of glitchless switching without using a complex synchronizing approach. In one example embodiment, a method includes generating a first and a second clock input signal. A select input signal is then synchronized with the first clock input signal and is capable of deselecting the first clock signal and delaying selection of the second clock signal. The first and second clock signals are then multiplexed with the select input signal to generate a multiplexed clock output signal corresponding to one of the clock input signals. A switch is then made from the first clock signal to the second clock signal without producing a glitch at the multiplexed output, the multiplexed output producing a momentary low pulse of width that is longer than the minimum of the low pulse of the first clock and low pulse of the second clock. The momentary low pulse is produced before an output signal corresponding to the second clock input clock signal is produced, the momentary low pulse width being a function of the selection delay of the select input signal.
In another example embodiment, a method of switching between asynchronous data inputs in a digital system is achieved without causing a glitch in the output. A first gated clock signal is generated by synchronizing a first gating select input signal to a first clock input signal. A second gated clock signal is generated by synchronizing a second gating select input signal to a second clock input signal. The first and second gated clock output signals are then multiplexed with a select input signal selection delay to generate a multiplexed clock output signal corresponding to one of the clock input signals. A switch is then made from the first gated clock input signal to the second gated clock input signal without producing a glitch at the multiplexed output, the multiplexed output producing a momentary low pulse of width that is longer than the minimum of the low pulse of the first clock and the low pulse of the second clock. The momentary low pulse is produced before an output signal corresponding to the second clock input clock signal is produced, the momentary pulse width being a function of the selection delay of the select input signal.
According to another aspect of the invention, a method of switching between asynchronous data inputs in a digital system is achieved without causing a glitch in the output. A first gated clock signal output is generated by synchronizing a first gating select input signal to the falling edge of a first clock input signal. A second gated clock signal output is generated by synchronizing a second gating select input signal to the falling edge of a second clock input signal. The first and second gated clock signals are then multiplexed with a selection input signal delay to generate a multiplexed output clock signal corresponding to one of the gated clock signals. A no-select guardband is generated between the first and second select input signals to synchronize switching from the first gated clock signal to the second gated clock signal such that momentarily the multiplexed clock output produces a pulse of duration longer than the minimum of the low pulse of the first and the low pulse of the second clock input signals. The momentary pulse is produced before an output signal corresponding to the second clock input clock signal is produced, the momentary low pulse width being a function of the selection delay of the select input signal.
In another aspect of the invention, a digital circuit is adapted for switching between two or more asynchronous data inputs without causing a glitch in the output. The circuit includes a first clock signal generator and a second clock signal generator adapted to generate a first and a second clock input signal, respectively. The circuit also includes a select input signal generator that generates a select signal that is synchronized with the first clock input signal, the select input signal generator capable of deselecting the first clock signal and delaying selection of the second clock signal. A digital multiplexer coupled to the clock signals and the select input signal multiplexes the first and second clock input signals with the select input signal selection delay to generate a clock output signal corresponding to one of the clock input signals. The circuit switches from the first clock input signal to the second clock input signal without producing a glitch at the multiplexed output, the multiplexed output producing a momentary low pulse of width that is longer than the minimum of the low pulse of the first clock signal and the low pulse of the second clock signal. The momentary low pulse is produced before an output signal is produced corresponding to the second clock input clock signal, the momentary low pulse width being a function of the selection delay of the select input signal.
In yet another aspect of the invention, a digital circuit is adapted for switching between two or more asynchronous data inputs without causing a glitch in the output. The circuit includes a first subcircuit for generating a first gated clock signal output signal synchronized by a first gating select input signal to a first clock input signal. A second subcircuit is included for generating a second gated clock signal by synchronizing a second gating select input signal to a second clock input signal. A digital multiplexer coupled to the first and second subcircuits is included for multiplexing the first and second gated clock output signals with a select input signal selection delay to generate a clock output signal corresponding to one of the clock input signals. A switching circuit coupled to the subcircuits is included for switching from the first gated clock input signal to the second gated clock input signal without producing a glitch at the multiplexed output, the multiplexed output producing a momentary low pulse of width that is longer than the mi
Callahan Timothy P.
Koninklijke Philips Electronics N.V. (KPEUV)
Nguyen Linh
LandOfFree
Method and apparatus for selecting a clock signal without... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for selecting a clock signal without..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for selecting a clock signal without... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2590550