Electrical computers and digital processing systems: processing – Instruction decoding
Reexamination Certificate
1999-02-01
2001-07-10
Shin, Christopher B. (Department: 2182)
Electrical computers and digital processing systems: processing
Instruction decoding
C710S004000, C710S200000, C365S185170
Reexamination Certificate
active
06260132
ABSTRACT:
BACKGROUND
The present invention concerns security with a computing system, and pertains particularly to secure address remapping.
Address decoders are often utilized for memory mapping within a computing system. For example, in systems which utilize the Advanced Microcontroller Bus Architecture (AMBA), an address decoder has the main function of centrally decoding the address provided by a master and selecting the appropriate bus slave. For more information on AMBA and the AMBA System Bus (ASB), see the web site for Advanced Risk Machines, Ltd., at WWW.ARM.com.
While integrated circuits often include secure features for the purpose of protecting against theft or misuse, there typically has been no secure features built into address decoders.
SUMMARY OF THE INVENTION
In accordance with the preferred embodiment of the present invention an address decoder includes a plurality of address decoder modules. Each address decoder module has a select line for each of a plurality of devices. Each of a plurality of XOR combination circuits performs a logic XOR function of all select lines for a single device from the plurality of devices. State control within the address decoder activates one address decoder module at a time.
In the preferred embodiment, each address decoder module is connected to an address bus portion of an AMBA System Bus (ASB). For example, when the address decoder is implemented for an AMBA System Bus (ASB), each address decoder module can be implemented as a standard ASB address decoder.
In the preferred embodiment, the state control asserts reset signals of all address decoder modules that are not activated. The permission access level required to access a device and the base address used to access a device can vary dependent on which address decoder module is activated. For example, different boot addresses for a processor could be accessed such that initially software could be booted (location
0
) from flash memory and then copied to random access memory (RAM) to be executed such that RAM now utilizes boot address (location
0
).
The present invention allows for the addition of security features into an address decoder. The use of multiple address decoder modules, as set out in the present invention, allows the re-use of a standard block to form a secure address decoder. Thus, in addition to an increase in security, the present invention allows for a simpler design when an address decoder needs to take into account state changes.
REFERENCES:
patent: 5377357 (1994-12-01), Nishigaki et al.
patent: 5581567 (1996-12-01), Chen et al.
patent: 5617559 (1997-04-01), Le et al.
patent: 5654923 (1997-08-01), Mizobata et al.
patent: 5657291 (1997-08-01), Podlesny et al.
patent: 5706407 (1998-01-01), Nakamura et al.
patent: 5963104 (1999-10-01), Buer
patent: 5964825 (1999-10-01), Seshan et al.
patent: 0608060A1 (1994-07-01), None
Shin Christopher B.
VLSI Technology Inc.
Weller Douglas L.
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