Method and apparatus for scrambling and descrambling video signa

Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry

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358117, 358122, H04N 716

Patent

active

045119198

ABSTRACT:
A system for scrambling a video signal that includes a vertical blanking interval of equalizing pulses spaced at half line intervals followed by serrations which are, in turn, followed by equalizing pulses spaced at half-line intervals and thereafter by horizontal pulses spaced from each other at intervals of two half-lines each. The scrambling includes (a) providing an unsuppressed interval in each field which extends through the first horizontal sync pulse preceded by a two half-line space and (b) suppressing horizontal sync pulses occurring after the first horizontal sync pulse preceded by a two half-line space. Descrambling includes (a) producing a reference pulse from the unsuppressed pulses occurring during the unsuppressed interval in each field--the reference pulses occurring at the same relative time in each field; (b) dividing the time between reference pulses to provide timing pulses corresponding to the horizontal sync pulse period; and (c) generating a descramble wave for each timing pulse occurring outside the unsuppressed interval--each descramble wave being applied to a scrambled signal to amplify and being timed to correspond with a suppressed horizontal sync pulse. The unsuppressed horizontal sync pulse(s) are used in determining the phase of the field being descrambled. Selective descrambling of scrambled composite video signals is achieved by inserting a flag (or flags) between equalizing pulses in the vertical blanking intervals during scrambling. A correlation between an inserted flag and a corresponding memory element in the descrambler must be detected before the descrambler will amplify the horizontal sync pulses which were suppressed during scrambling. Circuitry for determining the phase of a given field based on the position of the unsuppressed horizontal sync pulses and circuitry for (1) preventing descrambling of unscrambled signals and (2) performing descrambling for properly scrambled signals are also provided. Relatively tamperproof descrambler memory programming is also provided.

REFERENCES:
patent: 4068264 (1978-01-01), Pires
patent: 4222068 (1980-09-01), Thompson
patent: 4225884 (1980-09-01), Block et al.
patent: 4319273 (1982-03-01), Nossem
patent: 4338628 (1982-07-01), Payne et al.

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