Method and apparatus for scheduling test vectors in a...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C703S019000, C716S030000, C716S030000, C716S030000, C714S741000

Reexamination Certificate

active

07904286

ABSTRACT:
A computer implemented method, apparatus and computer program product for extending test coverage in a simulated multiple core integrated circuit. The simulator applies at a first time a first test vector on the simulated multiple core integrated circuit, the first test vector having a duration. The simulator may also apply a second test vector at a second time before the duration but substantially after the first time. The simulator can collect a response from the multiple core integrated circuit based on the first test vector and the second test vector.

REFERENCES:
patent: 4320509 (1982-03-01), Davidson
patent: 5650938 (1997-07-01), Bootehsaz et al.
patent: 6477673 (2002-11-01), Ferrant et al.
patent: 6651225 (2003-11-01), Lin et al.
patent: 6785873 (2004-08-01), Tseng
patent: 6833724 (2004-12-01), Binkley et al.
patent: 6934897 (2005-08-01), Mukherjee et al.
patent: 6980943 (2005-12-01), Aitken et al.
patent: 7043389 (2006-05-01), Plusquellic
patent: 7111198 (2006-09-01), Liu et al.
patent: 7460988 (2008-12-01), Higashi
“Between-Core Vector Overlapping for Test Cost Reduction in Core Testing”, Tsuyoshi Shinogi, 12thAsian Test Symposium (ATS '03). Nov. 16-19, 2003.
“A Reconfigurable Power-Conscience Core Wrapper and its Application to SOC Test Scheduling”, Eric Larsson and Zebo Peng, Embedded Systems Laboratory. Linkopings Universitet, Sweden. ITC International Test Conference, 2003.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for scheduling test vectors in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for scheduling test vectors in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for scheduling test vectors in a... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2781467

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.