Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
1999-01-08
2004-08-03
Kizou, Hassan (Department: 2662)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S229000, C370S389000, C370S390000, C370S412000, C370S415000, C370S416000, C370S432000
Reexamination Certificate
active
06771642
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of scheduling packets in a crossbar device.
2. Background
A typical crossbar switch includes multiple inputs and outputs. Packets that arrive at an input port are queued until the packet can be transferred to an output port. For purposes of the invention, there are two types of packets. A unicast packet contains addressing that selects only one output port of the packet switch. A multicast packet specifies multiple output ports of the packet switch.
When a unicast packet is pending, the packet's addressing information causes a unicast-packet-request signal to be sent the output port specified by the unicast packet. If the specified output port is free (or when it becomes free), a unicast arbiter for the output port selects and connects to a selected input port. The unicast packet is then transferred from the input port to the output port. Once the packet transfer is complete, the output port rearbitrates.
When a multicast is pending, a multicast-packet-request signals are sent by a multicast arbiter to each output port specified by the multicast packet at the input port. Once all the requested outputs are ready for the packet, the packet is simultaneously transferred to each output port. A single multicast arbiter is used for all the output ports.
One problem is related to how the output port should operate when both unicast- and multicast-packet-requests are pending at the output port. In a prior art implementation, the output has two states (unicast and multicast). Prior art packet switches can toggles between these states at the end of each transfer (if both unicast and multicast requests are pending), when the packet switch becomes totally blocked by pending multicast packets at the input ports, or in response to a timer. In prior art implementations, a synchronization delay occurs when the packet switch changes state. Thus, significant bandwidth utilization is lost every time the packet switch prepares to transfer a multicast packet. In addition, for the prior art implementations that switch state when the input ports are blocked, significant bandwidth utilization is lost as the input ports become blocked. Further, packets waiting for the blocked ports can be unacceptably delayed through the packet switch.
It would be advantageous to burst multiple multicast packets to increase the bandwidth utilization of the switch by reducing the number of multicast synchronization delays while limiting the delays caused by allowing the ports to become blocked by multicast packets.
SUMMARY OF THE INVENTION
The present invention reduces the number of multicast synchronization delays in a packet switch by determining the mix of packets pending at the input ports. When a sufficient number of multicast packets are ready for transferal, the packet switch preferably transmits a programmed number of multicast packets (or as many multicast packets that exist up to that programmed number). After transmitting these multicast packets, the packet switch resumes preferably transmitting unicast packets. Thus, the number of multicast synchronization delays is reduced over the prior art, the bandwidth utilization of the packet switch is correspondingly increased and the load due to multicast packets and unicast packet is balanced.
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Ngo Khuong Hoang
Seaver Terry R.
Cisco Technology Inc.
Hickman Palermo & Truong & Becker LLP
Kizou Hassan
Logsdon Joe
LandOfFree
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