Electrical computers and digital processing systems: multicomput – Computer-to-computer protocol implementing – Computer-to-computer data transfer regulating
Patent
1997-11-25
2000-03-14
Burgess, Glenton B.
Electrical computers and digital processing systems: multicomput
Computer-to-computer protocol implementing
Computer-to-computer data transfer regulating
370229, 374241, H04J 314
Patent
active
060386061
ABSTRACT:
Method and apparatus for returning packet acknowledgements from a packet receiving node to a packet sending node of a packet network. During a predefined initial startup phase of a packet connection between the sending and receiving nodes, an acknowledgement is returned to the sending node for every group of X packets received from the sending node. After the expiration of the initial startup phase, an acknowledgement is returned for every W-N packets received from the sending node. W represents the maximum number of packets that can be in transit on the connection at any given time, N is an integer less than W. If packet congestion occurs, the algorithm reverts to returning an acknowledgement for every group of X packets.
REFERENCES:
patent: 4646082 (1987-02-01), Engel et al.
patent: 5042029 (1991-08-01), Hayakawa
patent: 5245616 (1993-09-01), Olson
patent: 5432787 (1995-07-01), Chethik
Electronics and Communications in Japan, Part 1, vol. 77, No. 9, 1994 "Evaluation of Acknowledgement Methods for High-Speed Data Transmission", by Tadao Saito, Hitoshi Aida, Tadahiro Tomiyama, and Hong Fu, members of Faculty of Engineering, The University of Tokyo.
Tadao Saito et al. Evaluation of Acknowledgement Methods for High-Speed Data Transmission, Feb. 1993.
Britton Edward Glen
Brooks David Paul
Tracey Karen M.
Burgess Glenton B.
Herndon Jerry W.
Ho Chuong
International Business Machines Corp.
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