Method and apparatus for scheduling instructions in waves

Details Method and apparatus for scheduling instructions in waves Method and apparatus for scheduling instructions in waves

1997-01-08

2000-01-18

Maung, Zarni

Electrical computers and digital processing systems: processing

Instruction issuing

712205, 712206, 712216, 712217, G06F 938

Patent

active

060165405

ABSTRACT:
In a microprocessor, an Instruction scheduler 30 includes a dependency matrix 36 and a waiting buffer 34. A dependency determination unit 32 receives instructions to be executed, forwards the instructions to the waiting buffer 34, determines if any dependency exists between the instructions, and forwards the dependency information to the dependency matrix 36 in the form of a dependency vector 40. Dependency matrix 36 periodically determines whether any of the instructions contained in the waiting buffer 34 are ready to be executed, that is, no dependencies exist for that instruction. All identified instructions are then assigned to a current wave to be dispatched. The identified instructions are then dispatched for execution as execution resources become available. As each instruction is dispatched for execution in the waiting buffer 34, the dependency vector 40 for all dependent instructions is cleared for subsequent execution. However, until all instructions in the current wave are dispatched, no instructions in a subsequent wave may be dispatched. In this manner, an out-of-order processing scheme is implemented that efficiently accounts for data dependency between processed instructions.

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