Patent
1993-03-25
1998-10-06
Teska, Kevin J.
395706, G06F 900
Patent
active
058190880
ABSTRACT:
Improved parallelism in the generated schedules of basic blocks of a program being compiled is advantageously achieved by providing an improved scheduler to the code generator of a compiler targeting a multi-issue architecture computer. The improved scheduler implements the prior-art list scheduling technique with a number of improvements including differentiation of instructions into squeezed and non-squeezed instructions, employing priority functions that factor in the squeezed and non-squeezed instruction distinction for selecting a candidate instruction, tracking only the resources utilized by the non-squeezed instructions, and tracking the scheduling of the squeezed and non-squeezed instructions separately. When software pipelining is additionally employed to further increase parallelism in program loops, the improved scheduler factors only the non-squeezed instructions in the initial minimum schedule (initiation internal) size calculation.
REFERENCES:
patent: 5202975 (1993-04-01), Rasbold et al.
patent: 5202987 (1993-04-01), Bayer et al.
patent: 5202993 (1993-04-01), Tarsy et al.
patent: 5317734 (1994-05-01), Gupta
Touzeau, R.F., A Fortran Compiler for the EPS-164 Scientific Compiler, Proceedings of the ACM SIGPLAN '84 Symposium on Compiler Construction, ACM SIGPLAN Notices, vol. 19, No. 6, Jun. 1984.
Cohn, R., et al., Architecture and Compiler Tradeoffs For a Long Instruction Word Processor, Third International Conference on Architecture Support for Programming Languages and Operating System, ACM SIGPLAN Notices, vol. 24, Special Issue May 1989.
Borker, S. et al., iWarp: An Integrated Solution to High-Speed Parallel Computing, Proceedings of the Supercomputing Conference, Orlando, Fl., Nov. 14-18, 1988, The Computer Society of the IEEE.
Lam, M., Software Pipelining: An Effective Scheduling Technique For VLIW Machines, SIGPLAN '88 Conference n Programming Language Design and Implementation, Atlanta, Georgia, Jun. 22-24, 1988, ACM SIGPLAN Notices, vol. 23, No. 7, Jul. 1988.
Lam, M., A Systolic Array Optimizing Compiler, Ph.D. Thesis, Dept. of Computer Science, Carnegie Mellon University, CMU-CS-87-187, 1987.
Intel Corporation
Mohamed Ayni
Teska Kevin J.
LandOfFree
Method and apparatus for scheduling instructions for execution o does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for scheduling instructions for execution o, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for scheduling instructions for execution o will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-91343