Method and apparatus for scan testing of multi-phase logic

Details Method and apparatus for scan testing of multi-phase logic Method and apparatus for scan testing of multi-phase logic

1997-11-26

1999-02-16

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

058727957

ABSTRACT:
A method and apparatus for using a test signal being computed by applying a combinational test pattern generation tool to a model of the apparatus in which at least one of an at least one sequential device is modelled as a non-sequential device, the apparatus having a first scan cell configured to receive the test signal and drive a first signal in response to a first clock phase; a sequential logic block having the at least one sequential device, the sequential logic block being configured to generate a second signal, at least one of the at least one sequential device being a non-scan cell.

REFERENCES:
patent: 5748497 (1998-05-01), Scott et al.

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