Method and apparatus for scan testing an array in a data process

Details Method and apparatus for scan testing an array in a data process Method and apparatus for scan testing an array in a data process

1992-03-26

1995-05-09

Voeltz, Emanuel T.

Excavating

371 221, 3241581, G01R 3128, G06F 1100

Patent

active

054147140

ABSTRACT:
A method and apparatus for scan testing an array (20) in a data processing system (10). In one form, the present invention uses a scanning sense amplifier (22x) which can perform the three functions of a sense amplifier, a master test latch for scan testing, and a slave test latch for scan testing. Using one scanning sense amplifier (22x) to perform all three functions reduces the amount of circuitry required to scan test an array (20). The same stimulus is applied twice to the array (20); and half of the output data bits are scanned out during each application of the stimulus. One extra output data bit is also scanned out during each application of the stimulus. The end result is a reduction in the circuitry required to perform scan testing.

REFERENCES:
patent: 4477902 (1984-10-01), Puri et al.
patent: 4542509 (1985-09-01), Buchanan et al.
patent: 4697267 (1987-09-01), Wakai
patent: 4697279 (1987-09-01), Baratti et al.
patent: 4733405 (1988-03-01), Shimizume et al.
patent: 4833676 (1989-05-01), Koo
patent: 4862068 (1989-08-01), Kawashima et al.
patent: 4876704 (1989-10-01), Ozaki
patent: 4897838 (1990-01-01), Tateishi
patent: 5155432 (1992-10-01), Mahoney
patent: 5210759 (1993-05-01), DeWitt et al.
patent: 5252917 (1993-10-01), Kadowaki
patent: 5253255 (1993-10-01), Carbine
patent: 5285453 (1994-02-01), Gruodis
Eytan Hartung, Mike Gladden and Oded Yishay, "A Dual Pass Scan Mechanism for Minimizing Serial Scan Outputs", Jul. 1981, Motorola Technical Developments, vol. 13, pp. 14-15.
J. Lyon, M. Gladden, E. Hartung, E. Hoang, and K. Raghunathan, "Testability Features of the 68HC16Z1", 1991 IEEE Intl. Test Conference on Oct. 28, 1991; submitted after Jul. 16, 1991; pp. 5-6.
Dilip K. Bhavsar, "A New Economical Implementation for Scannable Flip-Flops in MOS", Jun. 1986, IEEE Design & Test, pp. 52-56.
Grady Giles, "Scan Path to Inject or Read Out Microcode", Oct. 1985, Motorola Technical Developments, vol. 5, p. 53.

Affiliated with

Also associated with

Rating

Method and apparatus for scan testing an array in a data process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for scan testing an array in a data process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for scan testing an array in a data process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1711472