Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2008-11-26
2011-10-11
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S118000, C716S122000, C716S135000, C716S139000, C438S106000, C257S678000
Reexamination Certificate
active
08037442
ABSTRACT:
One embodiment of the present invention provides a system that scales an I/O-cell placement during die-size optimization. During operation, the system starts by receiving an initial die-size for a die and an initial I/O-cell placement for a set of I/O cells. The system also receives a target die-size for the die. The system then determines die-size changes between the initial die-size and the target die-size. Next, the system identifies available spaces between the set of I/O cells in the initial I/O-cell placement. The system subsequently scales the initial I/O-cell placement based on the identified available spaces and the die-size changes to obtain a new I/O-cell placement which fits in the target die-size.
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Chang Douglas
Kaul Neeraj
Zou Peiqing
Do Thuan
Nguyen Nha
Park Vaughan Fleming & Dowler LLP
Synopsys Inc.
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