Method and apparatus for scaling I/O-cell placement during...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing

Reexamination Certificate

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Details

C716S118000, C716S122000, C716S135000, C716S139000, C438S106000, C257S678000

Reexamination Certificate

active

08037442

ABSTRACT:
One embodiment of the present invention provides a system that scales an I/O-cell placement during die-size optimization. During operation, the system starts by receiving an initial die-size for a die and an initial I/O-cell placement for a set of I/O cells. The system also receives a target die-size for the die. The system then determines die-size changes between the initial die-size and the target die-size. Next, the system identifies available spaces between the set of I/O cells in the initial I/O-cell placement. The system subsequently scales the initial I/O-cell placement based on the identified available spaces and the die-size changes to obtain a new I/O-cell placement which fits in the target die-size.

REFERENCES:
patent: 5155065 (1992-10-01), Schweiss
patent: 6457157 (2002-09-01), Singh et al.
patent: 7266789 (2007-09-01), Chung-Maloney et al.
patent: 2002/0199155 (2002-12-01), Kovacs-Birkas
patent: 2004/0006754 (2004-01-01), Sonohara
patent: 2006/0064660 (2006-03-01), Chung-Maloney et al.
patent: 2009/0051050 (2009-02-01), Bakker et al.

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