Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2001-08-09
2002-12-10
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189011, C365S194000, C365S189050, C365S239000
Reexamination Certificate
active
06493285
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a read data path structure in a double data rate (DDR) source-synchronous interface and, more particularly, to a software configurable read data path structure in a double data rate (DDR) synchronous dynamic random access memory (SDRAM) interface.
2. Description of the Related Art
Double Data Rate (DDR) synchronous dynamic random access memory (SDRAM) provides source synchronous read data in that a read data strobe (DQS) is propagated with read data. DDR read data is initially sampled in the DDR DQS clock domain and must be synchronized to the DDR memory controller internal clock domain for transfer. The DDR read data and DQS are propagated from the DDR memory to the DDR memory controller and derived from the DDR memory clock input, which is typically generated by the DDR memory controller and re-buffered and distributed either on-chip or off-chip. Thus, there is a potential for a widely varying range of read data and read DQS arrival times, across different implementations, relative to the memory controller's fixed internal clock domain(s).
Therefore, what is needed is a flexible DDR read data path structure to support a wide range of read data and DQS arrival times, adaptable to different implementations.
SUMMARY OF THE INVENTION
The present invention provides a read data path structure in a double data rate (DDR) source-synchronous interface such as a DDR synchronous random access memory (SDRAM) interface. The read data path structure comprises a first stage comprising a first flip-flop (FF) and a transparent latch (XL). The read data path structure also comprises a second stage comprising a second FF and a third FF. The input of the second FF is connected to the output of the first FF, whereas the input of the third FF is connected to the output of the XL.
The read data path structure further comprises a third stage comprising a fourth FF and a fifth FF. The input of the fourth FF is connected to the output of the second FF, whereas the input of the fifth FF is connected to the output of the third FF.
Additionally, the read data path structure comprises a first multiplexer having at least one input connected to the output of the first FF, at least one input connected to the output of the second FF, and at least one input connected to the output of the fourth FF. The first multiplexer is controlled by at least two bits of an SDRAM timing register.
The read data path structure further comprises a second multiplexer having at least one input connected to the output of the XL, at least one input connected to the output of the third FF, and at least one input connected to the output of the fifth FF. The second multiplexer is controlled by the at least two bits of the SDRAM timing register.
REFERENCES:
patent: 6243279 (2001-06-01), Maesako et al.
patent: 6266750 (2001-07-01), Demone et al.
patent: 6377501 (2002-04-01), Maesako et al.
patent: 2002/0010831 (2002-01-01), DeMone et al.
patent: 2002/0087768 (2002-07-01), Srikanth et al.
Carr Law Firm, L.L.P.
Carwell Robert M.
Nguyen Viet Q.
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