Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
1999-01-04
2001-03-20
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S293000
Reexamination Certificate
active
06204713
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to methods and structures for distributing clock signals within a semiconductor processor environment and, more particularly, to a methodology for growing and inserting clock trees on high-performance, low power application specific integrated circuit (ASIC) chips.
2. Description of the Related Art
Balanced clock distribution networks have historically fallen into four categories—meshes or grids, “H” or “I” trees, spines, and distributed buffers with or without balanced wiring. For example, FIG.
1
(
a
) illustrates an “H” tree, FIG.
1
(
b
) illustrates a spine structure and FIG.
1
(
c
) illustrates a mesh layout.
Mesh or grid methods are often simple to lay out, but have greater amounts of wire and higher capacitance than is necessary, which increases power requirements and reduces wireability. This problem is compounded when multiple clock domains are required, which is very common in a large variety of ASICs.
The “H” or “I” trees tend to have wide wires at their roots. Such wide wires are more susceptible to inductance at high frequency, which limits the latency or performance of the clock distribution network.
Conventional “H” trees are often driven from a localized source, causing noise or power supply dips. Often, a special analysis must be performed or the power buses must be strengthened in those regions to eliminate the noise or power supply dips. These steps can delay design schedules and limit floor plan changes.
Electromigration problems are also aggravated by localized wiring and sources. Pure “H” or “I” trees can also add more wire than is necessary.
Additionally, spines, or fishbones, have resistance/capacitance (RC) drops across them, which causes undesirable clock skew. Distributed buffers (with or without balanced routing) suffer from process variations and added latency, increasing skew and decreasing performance.
Further, inductance effects often go unnoticed in narrow single wires because the resistance is much greater than the inductive-reactance term. For clock networks, however, wide wires are often used to reduce resistance. If the transition time is fast enough (as is typically required at higher frequencies), the inductive-reactance term becomes significant with respect to the resistance. If this inductance is not considered, large errors in delays can result.
The following table shows the delay measured across a 10 mm wire segment with a 200 ps transition time input to the circuit. The delay is modeled, first without using inductance and then including inductance effects. The results presented in the following table show that the wire can be as much as 130 ps slower when inductance is considered.
Wire Width (&mgr;m)
RC Delay (ps)
RLC Delay (ps)
Difference (ps)
0.9
406.0
406.0
0
50
206.3
336.0
130
The difference in latency can result in skew if wide wires are used on some networks and narrow wires are used on other networks. Wide wires can have additional delay differences if return paths are not modeled correctly.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for designing a clock distribution network which does not add unnecessary wiring, avoids power supply drops (which is commonly associated with localized high-current-density clock circuits) and reduces high-frequency effects, such as inductance. The invention works on a large variety of chip sizes, package types, latch counts and operating frequencies. The invention allows a complete automated design of the clock network, including verification.
More specifically, the invention includes an integrated circuit chip comprising a plurality of first clock distribution sub-networks each including a first clock input for receiving a clock signal, each of the first clock distribution sub-networks having a first capacitance, as seen from the first clock input, substantially equivalent to others of the first clock distribution sub-networks, at least one first structured clock buffer having a first size based on a first load of the first clock distribution sub-networks, a first input pin, a first output pin and providing the clock signal to the first clock distribution sub-networks, the first clock input of each of the first clock distribution sub-networks being connected to the first output pin of the first structured clock buffer at generally equally spaced intervals along the first output pin measured from each other and from ends of the first output pin, a plurality of second clock distribution sub-networks each including, a second clock input for receiving the clock signal, each of the second clock distribution sub-networks having a second capacitance, as seen from the second clock input, substantially equivalent to others of the second clock distribution sub-networks, at least one second structured clock buffer having, a second size based on a second load of the second clock distribution sub-networks, a second output pin, a second input pin, and providing the clock signal to the second clock distribution sub-networks, the second clock input of each of the second clock distribution sub-networks being connected to the second output pin of the second structured clock buffer at generally equally spaced intervals along the second output pin measured from each other and from ends of the second output pin, and at least one third structured clock buffer having a third size, a third output pin, and providing the clock signal to the first structured clock buffer and the second structured clock buffer, the first input pin of the first structured clock buffer and the second input pin of the second structured clock buffer being, connected to the third output pin of the third structured clock buffer at generally equally spaced intervals along the third output pin measured from each other and from ends of the third output pin.
The first clock input comprises a single clock input and the second clock input comprises a single clock input. The first output pin comprises a single output pin and the first output pin extends along a length of the first structured clock buffer, the second output pin comprises a single output pin and the second output pin extends along a length of the second structured clock buffer, and the third output pin comprises a single output pin and the third output pin extends along a length of the third structured clock buffer.
The inventive integrated circuit chip includes a power grid, wherein the first structured clock buffer, the second structured clock buffer and the third structured clock buffer utilize an unmodified version of the power grid to drive the clock distribution sub-networks.
The first clock distribution sub-networks and the second clock distribution sub-networks each include at least one group of master and slave latches and at least one group of splitters for supplying the clock signal to a corresponding one of the at least one group of master and slave latches.
The first structured clock buffer has a first delay, the second structured clock buffer has the first delay and the third structured clock buffer has the first delay.
The invention also includes a scaleable structured clock buffer for driving clock distribution sub-networks, the structured clock buffer comprising at least one kernel comprising serially connected buffers and nodes positioned between the buffers and a number of the at least one kernel included within the structured clock buffer being based on a load of the clock distribution sub-networks to be driven by the structured clock buffer.
Each of the at least one kernel includes four serially connected buffers. The buffers comprise inverters. The structured clock buffer includes an output pin for connecting to the clock distribution sub-networks, wherein the output pin extends along a length of the structured clock buffer. The number of buffers included within each of the at least one kernel establishes a delay of the scaleable structured clock buffer.
The invention also includes a method of designin
Adams Janice M.
Carrig Keith M.
Gregor Roger P.
Menard Daniel R.
International Business Machines - Corporation
McGinn & Gibb PLLC
Nuton My-Trang
Shkurko, Esq. Eugene I.
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