Method and apparatus for routing a clock tree in an integrated c

Details Method and apparatus for routing a clock tree in an integrated c Method and apparatus for routing a clock tree in an integrated c

1996-03-26

1998-02-10

Tran, Minh-Loan

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

257211, 257777, 257776, H01L 23528

Patent

active

057172293

ABSTRACT:
A method and apparatus for routing a clock tree in an integrated circuit device. Prior art clock trees were routed entirely on an integrated circuit device, thereby increasing the size, complexity, and cost of the integrated circuit. The present invention provides for a design wherein the clock tree is partitioned into one or more local clock trees and a global clock tree. A local clock tree is defined as a cluster of clock sinks coupled together. The global clock tree is defined as the interconnect between the local clock tree and the clock source. The local clock tree is routed on a device layer of the integrated circuit. The global clock tree is routed on a package layer of the integrated circuit package. The package layer is coupled to the device layer through a plurality of contacts.

REFERENCES:
patent: 4769558 (1988-09-01), Bach
patent: 5013942 (1991-05-01), Nishimura et al.
patent: 5077676 (1991-12-01), Johnson et al.
patent: 5164817 (1992-11-01), Eisenstadt et al.
patent: 5221420 (1993-06-01), Covert et al.
patent: 5270592 (1993-12-01), Takahashi et al.
patent: 5467033 (1995-11-01), Yip et al.
patent: 5481209 (1996-01-01), Lim et al.
patent: 5497109 (1996-03-01), Honda et al.
patent: 5501006 (1996-03-01), Gehman, Jr. et al.
patent: 5570045 (1996-10-01), Erdal et al.
"Hierarchical Steiner Tree Construction in Uniform Orientations" M. Sarrafzadeh et al., IEEE Transactions on Computer-Aided Design, vol. 11, No. 9, Sep. 1992.
Qing Zhu; "Planar Clock Routing for Chip and Package Co-Design", IEEE Transactions on VLS1 Systems, Jun. 1995, pp. 0-33.

Affiliated with

Also associated with

Rating

Method and apparatus for routing a clock tree in an integrated c does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for routing a clock tree in an integrated c, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for routing a clock tree in an integrated c will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2079198