Method and apparatus for routing a clock tree in an integrated c

Details Method and apparatus for routing a clock tree in an integrated c Method and apparatus for routing a clock tree in an integrated c

1997-10-10

1999-02-02

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

257211, 257777, 257776, H01L 23528

Patent

active

058669248

ABSTRACT:
A method and apparatus for routing a clock tree in an integrated circuit device. Prior art clock trees were routed entirely on an integrated circuit device, thereby increasing the size, complexity, and cost of the integrated circuit. The present invention provides for a design wherein the clock tree is partitioned into one or more local clock trees and a global clock tree. A local clock tree is defined as a cluster of clock sinks coupled together. The global clock tree is defined as the interconnect between the local clock tree and the clock source. The local clock tree is routed on a device layer of the integrated circuit. The global clock tree is routed on a package layer of the integrated circuit package. The package layer is coupled to the device layer through a plurality of contacts.

REFERENCES:
patent: 5164817 (1992-11-01), Eisenstadt et al.
patent: 5270592 (1993-12-01), Takahashi et al.
patent: 5481209 (1996-01-01), Lim et al.
patent: 5570045 (1996-10-01), Erdal et al.

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