Horology: time measuring systems or devices – Time interval – Electrical or electromechanical
Reexamination Certificate
1999-06-04
2001-03-06
Miska, Vit (Department: 2816)
Horology: time measuring systems or devices
Time interval
Electrical or electromechanical
C368S120000, C327S141000, C327S161000, C375S354000, C375S371000
Reexamination Certificate
active
06198700
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to a method and apparatus for retiming test signals, and more particularly to a test signal retiming circuit that is resistant to timing variations.
2. Description of Related Art
Designers need an easy way to test in order to establish rapid prototyping of designs in a test environment. Test methodologies help a design engineer structure the simulation of a circuit. These test methodologies can efficiently reuse simulation stimuli and response for a real device under test. Also, these modern test approaches increase the efficiency of the engineer in a test environment.
The technological evolution in microelectronics has lead to the ever-increasing complexity of systems integrated on high density chips. Since development and test time should not grow at the same rate as the complexity, new design and test methods are needed.
There's a whole new category of devices that are troubling test engineers in the digital industry. Test systems availability and hardware dependencies are a few limitations that plague a test engineer. To deal with the limitations, many hardware manufactures prefer digital testers as part of their automated test equipment. They also want a consistent testing environment that provides all the digital performance they need and reduces test development time by providing a consistent digital test methodology for all tests.
Manufacturer's need an integrated solution for the high-throughput production test coverage required to ensure quality in digital-dominant integrated circuits. Testing such devices requires the full functionality of a digital tester. Attributes such as high pin counts, high data rates and timing flexibility, combined with digital test methodologies now need to be coupled with the ability to test digital cells.
A digital testing devices has several advantages. It allows the designer to check for design-for-testability success at a much earlier stage during the manufacturing process. Also, errors are discovered before mass production is initiated. This greatly improves the likelihood of a correct designs earlier in an engineering effort.
One important aspect of digital test systems is the ability of the system provide a timing reference signal to detect correct digital output when sampling an output signal. The device must be insensitive to external stimuli and variations in hardware performance. During digital testing using automated test equipment, device inputs are driven by a set of digital vectors and device outputs are strobed by a tester and compared to reference data. Depending on the functionality, design implementation, process variation, tester, loadboard, interface hardware and output data detection, there are significant variations in clock skew and data arrival during clock periods.
For example, a tremendous problem in industrial digital testing is to identify variability of the data arrival and clock skew during the output data detection. Another problem is positioning the test timing strobe to detect a rise and fall of a signal edge consistently. Nevertheless, non-consistency directly effects repeatability of the test process, which in turn presents a problem for high volume production.
With increases in device operating frequencies and reduction in component size, this task becomes even more difficult. Deep submicron processes create further sources of timing variability. Test periods are reduced significantly without improvements in output data detection, and device timing accuracy approaches the automatic test equipment timing resolution.
It can be seen then that there is a need for test signal retiming circuit that consistently detects valid output data.
It can also be seen that there is a need for a test signal retiming circuit that is resistant to timing variations.
It can also be seen that there is a need for a test signal retiming circuit that ensures that the output data consistently is synchronized with the automatic test equipment.
SUMMARY OF THE INVENTION
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a test signal retiming circuit that is resistant to timing variations.
The present invention solves the above-described problems by providing a test signal retiming circuit that consistently detects the rise and fall of the signal edge by providing an intermediate test circuit. This test circuit incorporates a test reference clock allowing the output data from a device under test to be valid for a complete test cycle.
A method in accordance with the principles of the present invention includes capturing an input signal to produce a first output signal in response to a first reference signal, generating a second output signal in response to the first output signal and a second reference signal, wherein the second output signal is resistant to an input signal timing variation and verifying that the second output signal appears at an output at a predetermined time.
Other embodiments of a system in accordance with the principles of the invention may include alternative or optional additional aspects. One such aspect of the present invention is that the capturing the input signal to produce the first output signal further includes acquiring the input signal in a first buffer in response to the first reference signal and transferring the acquired input signal from the first buffer to a second buffer in response to the first reference signal.
Another aspect of the present invention is that the first reference signal is generated by a system clock, the first reference signal having a rising edge and a falling edge, the rising edge gating the input signal from the first buffer and the falling edge gating the input signal from the second buffer.
Another aspect of the present invention is that the system clock further produces a timing signal for a component under test.
Another aspect of the present invention is that the generating a secodn output signal further includes the first output signal from the second buffer to a third buffer in response to the second reference signal to produce the second output signal.
Another aspect of the present invention is that the second reference signal is a test clock, the test clock having a rising edge and a falling edge, the rising edge of the test signal signal gating the first output signal into the third buffer to produce the second output signal.
Another aspect of the present invention is that the test clock produces a timing signal, the timing signal being used to compare the second output thereto.
Another aspect of the present invention is that the verifying further includes comparing a predetermined signal to the second output signal and determining if the second output signal matches the predetermined signal.
Another aspect of the present invention is that the determining if the second output signal matches the predetermined signal further includes sampling the second output signal at a predetermined period to compare the sample to the predetermined signal.
Another aspect of the present invention is that the second output signal includes minimal skew.
Another aspect of the present invention is that the skew of the second output signal further includes a plurality of clock and data skews.
These and various other advantages and features of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and form a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further path hereof, and to accompanying descriptive matter, in which there are illustrated and described specific examples of an apparatus in accordance with the invention.
REFERENCES:
patent: 5036529 (1991-07-01), Shin
patent: 5689533 (1997-11-01), Brauns et al.
patent: 5886552 (1999-03-01), Chai et al.
Level One Communications Inc.
Merchant & Gould P.C.
Miska Vit
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